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@ARTICLE{Kuriakose:1050050,
      author       = {Kuriakose, Neethu and Ashok, Arun and Grewing, Christian
                      and Zambanini, André and van Waasen, Stefan},
      title        = {2{T}1{R} {R}egulated {M}emristor {C}onductance {C}ontrol
                      {A}rray {A}rchitecture for {N}euromorphic {C}omputing using
                      28nm {CMOS} {T}echnology},
      reportid     = {FZJ-2025-05764, arXiv:2505.12830},
      year         = {2025},
      abstract     = {Memristors are promising devices for scalable and low
                      power, in-memory computing to improve the energy efficiency
                      of a rising computational demand. The crossbar array
                      architecture with memristors is used for vector matrix
                      multiplication (VMM) and acts as kernels in neuromorphic
                      computing. The analog conductance control in a memristor is
                      achieved by applying voltage or current through it. A basic
                      1T1R array is suitable to avoid sneak path issues but suffer
                      from wire resistances, which affects the read and write
                      procedures. A conductance control scheme with a regulated
                      voltage source will improve the architecture and reduce the
                      possible potential divider effects. A change in conductance
                      is also possible with the provision of a regulated current
                      source and measuring the voltage across the memristors. A
                      regulated 2T1R memristor conductance control architecture is
                      proposed in this work, which avoids the potential divider
                      effect and virtual ground scenario in a regular crossbar
                      scheme, as well as conductance control by passing a
                      regulated current through memristors. The sneak path current
                      is not allowed to pass by the provision of ground potential
                      to both terminals of memristors.},
      cin          = {PGI-4},
      cid          = {I:(DE-Juel1)PGI-4-20110106},
      pnm          = {5234 - Emerging NC Architectures (POF4-523)},
      pid          = {G:(DE-HGF)POF4-5234},
      typ          = {PUB:(DE-HGF)25},
      eprint       = {2505.12830},
      howpublished = {arXiv:2505.12830},
      archivePrefix = {arXiv},
      SLACcitation = {$\%\%CITATION$ = $arXiv:2505.12830;\%\%$},
      url          = {https://juser.fz-juelich.de/record/1050050},
}