001050052 001__ 1050052
001050052 005__ 20251219170355.0
001050052 037__ $$aFZJ-2025-05766
001050052 041__ $$aEnglish
001050052 1001_ $$0P:(DE-Juel1)176775$$aKrystofiak, Lukas$$b0$$ufzj
001050052 1112_ $$a8th International Conference on Memristive Materials, Devices & Systems$$cEdinburgh$$d2025-10-13 - 2025-10-16$$gMEMRISYS 2025$$wUK
001050052 245__ $$aA scaling-friendly memristor-based leaky integrate-and-fire circuit in a TSMC 28nm process technology
001050052 260__ $$c2025
001050052 3367_ $$033$$2EndNote$$aConference Paper
001050052 3367_ $$2DataCite$$aOther
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001050052 3367_ $$0PUB:(DE-HGF)6$$2PUB:(DE-HGF)$$aConference Presentation$$bconf$$mconf$$s1766159876_4886$$xAfter Call
001050052 520__ $$aSpiking neural networks mimic the way the human brain processes data and excel in efficiency. With the advent of the memristor, foundations are laid for scalable and low-power integrated electronic implementations. Key is the small form factor of the memristor and its ability to passively retain a multilevel state.To investigate the feasibility of memristor-based spiking neural networks, a first chip is developed containing all necessary circuits to read and write memristors. It will be connected via chip-to-chip bonding wires to a 3 by 3 memristor array. In this abstract the focus is on the implemented leaky integrate-and-fire circuit (LIF).While the memristors act as the synapses of the neural network, the neurons are modeled as current-based RC LIF circuits. Previous implementations minimized the current to reduce the area footprint as much as possible which is dominated by the capacitor size[1][2]. This is prone to process variations, especially in smaller technology nodes. Thus, precise analog calibrations are needed for every single neuron. This complicates scaling spiking neuronal networks. A novel approach reduces the width of incoming spikes in the LIF circuit to a fraction of the original by an additional duty-cycle element which is controlled by ɸPulse. This is generated globally by a reference clock with an adjustable duty cycle and then distributed to all LIF elements minimizing the wiring and biasing overhead. Additionally, the operation time frame of the SNN can be tuned through this. The duty cycle approach effectively transforms the system to the time-discrete domain, but with the very high switching speeds, enabled by a 28 nm process technology, compared to the intended operating speed of the neural network it can be regarded as pseudo time-continuous.A first tapeout in a 28nm process technology is scheduled for September 2025 and post-layout simulations will be shown.
001050052 536__ $$0G:(DE-HGF)POF4-5234$$a5234 - Emerging NC Architectures (POF4-523)$$cPOF4-523$$fPOF IV$$x0
001050052 8564_ $$uhttps://www.memrisys2025.org/Home/Welcome
001050052 8564_ $$uhttps://juser.fz-juelich.de/record/1050052/files/Abstract_MEMRISYS%202025_LIF.pdf$$yRestricted
001050052 9101_ $$0I:(DE-588b)5008462-8$$6P:(DE-Juel1)176775$$aForschungszentrum Jülich$$b0$$kFZJ
001050052 9131_ $$0G:(DE-HGF)POF4-523$$1G:(DE-HGF)POF4-520$$2G:(DE-HGF)POF4-500$$3G:(DE-HGF)POF4$$4G:(DE-HGF)POF$$9G:(DE-HGF)POF4-5234$$aDE-HGF$$bKey Technologies$$lNatural, Artificial and Cognitive Information Processing$$vNeuromorphic Computing and Network Dynamics$$x0
001050052 9141_ $$y2025
001050052 9201_ $$0I:(DE-Juel1)PGI-4-20110106$$kPGI-4$$lIntegrated Computing Architectures$$x0
001050052 980__ $$aconf
001050052 980__ $$aEDITORS
001050052 980__ $$aVDBINPRINT
001050052 980__ $$aI:(DE-Juel1)PGI-4-20110106
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