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| Home > Publications database > CMOS-Memristive Dendrite Architecture for Reliable Temporal Pattern Recognition |
| Conference Presentation (After Call) | FZJ-2026-00332 |
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2025
Abstract: Temporal sequences of spiking activity serve as a fundamental medium through which the brain encodes and processes information. Extracting meaningful temporal structure from these sequences is a core computational task for both biological and artificial intelligent systems1. Recent advances in brain-inspired computing have introduced the concept of dendritic plateau computation (DPC)—a mechanism arising from the interaction of localized plateau potentials across functionally compartmentalized dendritic branches2,3. Inspired by this biological paradigm, we propose a memristive dendritic architecture incorporating a multi-compartmental neuron model. In this design, critical temporal features are encoded through tunable resistances at memristive crosspoints4, while the adjustable retention times of volatile memristors5,6 are leveraged to implement plateau durations, allowing temporal dynamics to be adapted to application-specific requirements.We demonstrate that a single neuron within this architecture achieves temporal selectivity, even in the presence of timing variability. Additionally, we construct a two-layer network of neuron populations for sequence classification, a task complicated by intra-sequence timing variation. Our results show that the proposed memristive DPC hardware accurately classifies temporal sequences without the need to store auxiliary features for handling timing variability, thus reducing network size and complexity. This work highlights the potential of active dendritic processes as fundamental computational primitives for realizing efficient, brain-inspired hardware systems.
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