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@ARTICLE{Padilla:111884,
      author       = {Padilla, J.L. and Knoll, L. and Gámiz, F. and Zhao, Q.T.
                      and Godoy, A. and Mantl, S.},
      title        = {{S}imulation of {F}abricated 20-nm {S}chottky {B}arrier
                      {MOSFET}s on {SOI}:{I}mpact of barrier {L}owering},
      journal      = {IEEE Transactions on Electron Devices},
      volume       = {59},
      issn         = {0018-9383},
      reportid     = {PreJuSER-111884},
      pages        = {1320 - 1327},
      year         = {2012},
      note         = {Manuscript received October 21, 2011; revised December 20,
                      2011 and January 13, 2012; accepted February 2, 2012. Date
                      of publication March 9, 2012; date of current version April
                      25, 2012. This work was supported in part by the Junta de
                      Andalucia under Research Project TIC2010-6902 and in part by
                      the Spanish Government under Research Projects FIS2008-05805
                      and TEC2008-06758-C02-01. The review of this paper was
                      arranged by Editor Y. Momiyama.},
      abstract     = {In this paper, we develop a procedure to include in device
                      simulators the barrier lowering (BL) effects that appear in
                      the drain and source contacts of Schottky barrier MOSFETs
                      (SB-MOSFETs). We have checked it reproducing experimental
                      results of 20-nm gate-length SB-MOSFETs with NiSi and
                      epitaxial NiSi2 S/D contacts. We make use of the
                      Wentzel-Kramers-Brillouin (WKB) approximation to get the
                      tunneling probabilities through the lowered barriers along
                      with an appropriate calibration of the effective masses
                      which compensates to a large extent the lack of accuracy of
                      the WKB model when diverting from the "wide barrier"
                      assumption. A vertical discretization of the channel is also
                      included to allow the barrier height dependence on the depth
                      inside the channel. We show that corrected simulations
                      including this effect describe in a very accurate way the
                      behavior of these devices. We also check that the striking
                      experimental observation of tunneling current reduction at
                      very short gate lengths is also obtained, in contrast to the
                      scaling behavior of conventional MOSFETs. We successfully
                      explain this fact invoking the modification of the potential
                      inside the channel, i.e., the overlapping of source and
                      drain potential profiles leads to an increase of its total
                      value even though BL mechanisms tend to decrease it in the
                      vicinity of the contacts.},
      keywords     = {J (WoSType)},
      cin          = {JARA-FIT / PGI-9},
      cid          = {$I:(DE-82)080009_20140620$ / I:(DE-Juel1)PGI-9-20110106},
      pnm          = {Grundlagen für zukünftige Informationstechnologien},
      pid          = {G:(DE-Juel1)FUEK412},
      shelfmark    = {Engineering, Electrical $\&$ Electronic / Physics, Applied},
      typ          = {PUB:(DE-HGF)16},
      UT           = {WOS:000303202900013},
      doi          = {10.1109/TED.2012.2187657},
      url          = {https://juser.fz-juelich.de/record/111884},
}