Journal Article PreJuSER-111884

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Simulation of Fabricated 20-nm Schottky Barrier MOSFETs on SOI:Impact of barrier Lowering

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2012

IEEE Transactions on Electron Devices 59, 1320 - 1327 () [10.1109/TED.2012.2187657]

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Abstract: In this paper, we develop a procedure to include in device simulators the barrier lowering (BL) effects that appear in the drain and source contacts of Schottky barrier MOSFETs (SB-MOSFETs). We have checked it reproducing experimental results of 20-nm gate-length SB-MOSFETs with NiSi and epitaxial NiSi2 S/D contacts. We make use of the Wentzel-Kramers-Brillouin (WKB) approximation to get the tunneling probabilities through the lowered barriers along with an appropriate calibration of the effective masses which compensates to a large extent the lack of accuracy of the WKB model when diverting from the "wide barrier" assumption. A vertical discretization of the channel is also included to allow the barrier height dependence on the depth inside the channel. We show that corrected simulations including this effect describe in a very accurate way the behavior of these devices. We also check that the striking experimental observation of tunneling current reduction at very short gate lengths is also obtained, in contrast to the scaling behavior of conventional MOSFETs. We successfully explain this fact invoking the modification of the potential inside the channel, i.e., the overlapping of source and drain potential profiles leads to an increase of its total value even though BL mechanisms tend to decrease it in the vicinity of the contacts.

Keyword(s): J ; Barrier lowering (auto) ; metallic source/drain (S/D) (auto) ; nanotechnology (auto) ; Schottky barriers (auto) ; semiconductor device modeling (auto) ; Wentzel-Kramers-Brillouin (WKB) method (auto)


Note: Manuscript received October 21, 2011; revised December 20, 2011 and January 13, 2012; accepted February 2, 2012. Date of publication March 9, 2012; date of current version April 25, 2012. This work was supported in part by the Junta de Andalucia under Research Project TIC2010-6902 and in part by the Spanish Government under Research Projects FIS2008-05805 and TEC2008-06758-C02-01. The review of this paper was arranged by Editor Y. Momiyama.

Contributing Institute(s):
  1. Halbleiter-Nanoelektronik (PGI-9)
  2. Jülich-Aachen Research Alliance - Fundamentals of Future Information Technology (JARA-FIT)
Research Program(s):
  1. Grundlagen für zukünftige Informationstechnologien (P42)

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 Record created 2012-11-16, last modified 2018-02-11



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