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@ARTICLE{Urban:11288,
      author       = {Urban, C. and Sandow, C. and Zhao, Q. T. and Knoch, J. and
                      Lenk, S. and Mantl, S.},
      title        = {{S}ystematic study of {S}chottky barrier {MOSFET}s with
                      dopant segregation on thin-body {SOI}},
      journal      = {Solid state electronics},
      volume       = {54},
      issn         = {0038-1101},
      address      = {Oxford [u.a.]},
      publisher    = {Pergamon, Elsevier Science},
      reportid     = {PreJuSER-11288},
      pages        = {185 - 190},
      year         = {2010},
      note         = {Record converted from VDB: 12.11.2012},
      abstract     = {In this paper. we present a detailed study of
                      nickel-silicide source and drain Schottky barrier MOSFETs on
                      thin-body silicon-on-insulator. We use silicidation induced
                      dopant segregation to lower the effective Schottky barrier
                      height of NiSi source/drain to channel contacts. p-Type
                      Schottky barrier MOSFFTs with boron segregation and n-type
                      Schottky barrier MOSFETs with arsenic segregation show
                      substantially improved electrical characteristics when
                      compared to devices without dopant segregation. An inverse
                      subthreshold slope close to the thermal limit and
                      on-currents which are one order of magnitude higher than for
                      Schottky barrier MOSFETs without dopant segregation are
                      observed for devices with dopant segregation. A statistical
                      analysis of Schottky barrier MOSFETs with dopant segregation
                      reveals a strong dependence on the doping concentration of
                      the electrical performance of both, p- and n-type devices.
                      Source and drain resistances of 560 Omega mu m are extracted
                      for n-type devices on 30 nm thick silicon-on-insulator. (C)
                      2009 Elsevier Ltd. All rights reserved},
      keywords     = {J (WoSType)},
      cin          = {IBN-1 / JARA-FIT},
      ddc          = {530},
      cid          = {I:(DE-Juel1)VDB799 / $I:(DE-82)080009_20140620$},
      pnm          = {Grundlagen für zukünftige Informationstechnologien},
      pid          = {G:(DE-Juel1)FUEK412},
      shelfmark    = {Engineering, Electrical $\&$ Electronic / Physics, Applied
                      / Physics, Condensed Matter},
      typ          = {PUB:(DE-HGF)16},
      UT           = {WOS:000275691400017},
      doi          = {10.1016/j.sse.2009.12.017},
      url          = {https://juser.fz-juelich.de/record/11288},
}