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@INPROCEEDINGS{Menouni:135288,
author = {Menouni, M and Arutinov, D and Backhaus, M and Barbero, M
and Beccherle, R and Breugnon, P and Caminada, L and Dube, S
and Darbo, G and Fleury, J and Fougeron, D and
Garcia-Sciveres, M and Gensolen, F and Gnani, D and Gonella,
L and Gromov, V and Hemperek, T and Jensen, F and
Karagounis, M and Kluit, R and Krueger, H and Kruth, A and
Lu, Y and Rozanov, A and Schipper, J -D and Zivkovic, V and
Mekkaoui, A},
title = {{SEU} tolerant memory design for the {ATLAS} pixel readout
chip},
journal = {Journal of Instrumentation},
volume = {8},
number = {02},
issn = {1748-0221},
address = {London},
publisher = {Inst. of Physics},
reportid = {FZJ-2013-03232},
pages = {C02026 - C02026},
year = {2013},
abstract = {The FE-I4 chip for the B-layer upgrade is designed in a 130
nm CMOS process. For this design, configuration memories are
based on the DICE latches where layout considerations are
followed to improve the tolerance to SEU. Tests have shown
that DICE latches for which layout approaches are adopted
are 30 times more tolerant to SEU than the standard DICE
latches. To prepare for the new pixel readout chip planned
for the future upgrades, a prototype chip containing 512
pixels has been designed in a 65 nm CMOS process and a new
approach is adopted for SEU tolerant latches. Results in
terms of SEU and TID tolerance are presented.},
date = {17092012},
organization = {Topical Workshop on Electronics for
Particle Physics 2012, Oxford (UK),
17092012 - 21092012},
cin = {ZEA-2},
ddc = {610},
cid = {I:(DE-Juel1)ZEA-2-20090406},
pnm = {899 - ohne Topic (POF2-899)},
pid = {G:(DE-HGF)POF2-899},
typ = {PUB:(DE-HGF)8 / PUB:(DE-HGF)16},
UT = {WOS:000315672700026},
doi = {10.1088/1748-0221/8/02/C02026},
url = {https://juser.fz-juelich.de/record/135288},
}