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| Hauptseite > Publikationsdatenbank > Submission of the first fullscale prototype chip for upgraded ATLAS pixel detector at LHC, FE-I4A |
| Hauptseite > Publikationsdatenbank > Submission of the first fullscale prototype chip for upgraded ATLAS pixel detector at LHC, FE-I4A |
| Contribution to a conference proceedings/Journal Article | FZJ-2013-03233 |
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2010
North-Holland Publ. Co.
Amsterdam
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Please use a persistent id in citations: doi:10.1016/j.nima.2010.11.131
Abstract: A new ATLAS pixel chip FE-I4 is being developed for use in upgraded LHC luminosity environments, including the near-term Insertable B-Layer (IBL) upgrade. FE-I4 is designed in a 130 nm CMOS technology, presenting advantages in terms of radiation tolerance and digital logic density compared to the View the MathML source0.25μm CMOS technology used for the current ATLAS pixel IC, FE-I3. The FE-I4 architecture is based on an array of 80×336 pixels, each View the MathML source50×250μm2, consisting of analog and digital sections. In the summer 2010, a first full scale prototype FE-I4A was submitted for an engineering run. This IC features the full scale pixel array as well as the complex periphery of the future full-size FE-I4. The FE-I4A contains also various extra test features which should prove very useful for the chip characterization, but deviate from the needs for standard operation of the final FE-I4 for IBL. In this paper, focus will be brought to the various features implemented in the FE-I4A submission, while also underlining the main differences between the FE-I4A IC and the final FE-I4 as envisioned for IBL.
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