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| Hauptseite > Publikationsdatenbank > Performance Analysis and Enabling of the RayBen Code for the Intel® MIC Architecture > print |
| Hauptseite > Publikationsdatenbank > Performance Analysis and Enabling of the RayBen Code for the Intel® MIC Architecture > print |
| 001 | 187427 | ||
| 005 | 20210129215020.0 | ||
| 024 | 7 | _ | |a 2128/8332 |2 Handle |
| 037 | _ | _ | |a FZJ-2015-01092 |
| 041 | _ | _ | |a English |
| 088 | 1 | _ | |a PRACE WP 129 |
| 088 | _ | _ | |a PRACE WP 129 |2 Other |
| 100 | 1 | _ | |a Schnurpfeil, Alexander |0 P:(DE-Juel1)132257 |b 0 |e Corresponding Author |
| 245 | _ | _ | |a Performance Analysis and Enabling of the RayBen Code for the Intel® MIC Architecture |
| 260 | _ | _ | |c 2014 |b PRACE Consortium Partners |
| 300 | _ | _ | |a 9 p. |
| 336 | 7 | _ | |a Report |b report |m report |0 PUB:(DE-HGF)29 |s 1422601152_8068 |2 PUB:(DE-HGF) |
| 336 | 7 | _ | |a Output Types/Report |2 DataCite |
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| 336 | 7 | _ | |a REPORT |2 ORCID |
| 336 | 7 | _ | |a Report |0 10 |2 EndNote |
| 336 | 7 | _ | |a report |2 DRIVER |
| 520 | _ | _ | |a The subject of this project is the analysis and enabling of the RayBen code, which implements a finite difference scheme for the simulation of turbulent Rayleigh-Bénard convection in a closed cylindrical cell, for the Intel® Xeon Phi coprocessor architecture. After a brief introduction to the physical background of the code, the integration of Rayben into the benchmarking environment JuBE is discussed. The structure of the code is analysed through its call graph. The most performance-critical routines were identified. A detailed analysis of the OpenMP parallelization revealed several race conditions which were eliminated. The code was ported to the JUROPA cluster at the Jülich Supercomputing as well as to the EURORA cluster at CINECA. The performance of the code is discussed using the results of pure MPI and hybrid MPI/OpenMP benchmarks. It is shown that RayBen is a memory-intensive application that highly benefits from the MPI parallelization. The offloading mechanism for the Intel® MIC architecture lowers considerably the performance while the use of binaries that run exclusively on the coprocessor show a satisfactory performance and a scalability which is comparable to the CPU. |
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| 700 | 1 | _ | |a Janetzko, Florian |0 P:(DE-Juel1)132149 |b 1 |u fzj |
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| 700 | 1 | _ | |a Emran, M. S. |0 P:(DE-HGF)0 |b 4 |
| 700 | 1 | _ | |a Schumacher, J. |0 P:(DE-HGF)0 |b 5 |
| 773 | _ | _ | |y 2014 |
| 856 | 4 | _ | |u http://www.prace-ri.eu/IMG/pdf/wp129.pdf |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/187427/files/FZJ-2015-01092.pdf |y OpenAccess |
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