Contribution to a conference proceedings/Contribution to a book

FZJ-2015-02451

http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png IBM 3090 Memory Access: Measurement and Simulation

Homberg, W. (Corresponding Author)FZJ* ; Hake, J.-F.FZJ* ; Gürich, W.FZJ*

1991

Abstract: The imbalance between processor speed and memory access time is one characteristic issue of modern high-speed computers sometimes leading to a bottleneck for algorithms with a great amount of memory traffic. Different architectural concepts are provided to diminish this effect. One attempt to reach this goal is the implementation of a hierarchical memory structure. On IBM computers, this hierarchy includes CPU, cache (high-speed buffer), main memory, and paging devices (e.g. expanded storage and disks).A model focusing on the memory architecture of the IBM 3090 family is developed and the behavior of sequential algorithms with respect to cache and translation lookaside buffer (TLB) is considered. For a given sequence of memory references the numbers of cache misses and TLB misses are calculated and the amount of CPU time consumed by these effects can be estimated. Parameters describing the buffer size, line length, the number of sets, and different replacement algorithms are taken into account.The model is verified by studying the performance of application-oriented programs from numerical linear algebra with a known memory access pattern. Jobs were run on IBM 3090 computers differing in cache size and processor cycle time. The measured CPU time consumption is compared with the predicted results showing that measurement and simulation are in good agreement.

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Contributing Institute(s):

1. Zentralinstitut für Angewandte Mathematik (ZAM)
2. Jülich Supercomputing Center (JSC)

Research Program(s):

1. 899 - ohne Topic (POF2-899) (POF2-899)

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