% IMPORTANT: The following is UTF-8 encoded.  This means that in the presence
% of non-ASCII characters, it will not work with BibTeX 0.99 or older.
% Instead, you should use an up-to-date BibTeX implementation like “bibtex8” or
% “biber”.

@INPROCEEDINGS{Homberg:189273,
      author       = {Homberg, Wilhelm and Hake, Jürgen-Fr. and Gürich,
                      Wolfgang},
      title        = {{IBM} 3090 {M}emory {A}ccess: {M}easurement and
                      {S}imulation},
      reportid     = {FZJ-2015-02451},
      pages        = {14 p.},
      year         = {1991},
      comment      = {Proceedings ot the SHARE Europe (SEAS) Spring Meeting 1991},
      booktitle     = {Proceedings ot the SHARE Europe (SEAS)
                       Spring Meeting 1991},
      abstract     = {The imbalance between processor speed and memory access
                      time is one characteristic issue of modern high-speed
                      computers sometimes leading to a bottleneck for algorithms
                      with a great amount of memory traffic. Different
                      architectural concepts are provided to diminish this effect.
                      One attempt to reach this goal is the implementation of a
                      hierarchical memory structure. On IBM computers, this
                      hierarchy includes CPU, cache (high-speed buffer), main
                      memory, and paging devices (e.g. expanded storage and
                      disks).A model focusing on the memory architecture of the
                      IBM 3090 family is developed and the behavior of sequential
                      algorithms with respect to cache and translation lookaside
                      buffer (TLB) is considered. For a given sequence of memory
                      references the numbers of cache misses and TLB misses are
                      calculated and the amount of CPU time consumed by these
                      effects can be estimated. Parameters describing the buffer
                      size, line length, the number of sets, and different
                      replacement algorithms are taken into account.The model is
                      verified by studying the performance of application-oriented
                      programs from numerical linear algebra with a known memory
                      access pattern. Jobs were run on IBM 3090 computers
                      differing in cache size and processor cycle time. The
                      measured CPU time consumption is compared with the predicted
                      results showing that measurement and simulation are in good
                      agreement.},
      month         = {Apr},
      date          = {1991-04-08},
      organization  = {SHARE Europe (SEAS) Spring Meeting
                       1991, Lausanne (Switzerland), 8 Apr
                       1991 - 12 Apr 1991},
      cin          = {ZAM / JSC},
      cid          = {I:(DE-Juel1)VDB62 / I:(DE-Juel1)JSC-20090406},
      pnm          = {899 - ohne Topic (POF2-899)},
      pid          = {G:(DE-HGF)POF2-899},
      typ          = {PUB:(DE-HGF)8 / PUB:(DE-HGF)7},
      url          = {https://juser.fz-juelich.de/record/189273},
}