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Contribution to a conference proceedings/Contribution to a book | FZJ-2015-02751 |
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2015
Springer International Publishing
Cham
ISBN: 978-3-319-17247-7 (print), 978-3-319-17248-4 (electronic)
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Please use a persistent id in citations: doi:10.1007/978-3-319-17248-4_2
Abstract: With POWER8 a new generation of POWER processors became available. This architecture features a moderate number of cores, each of which expose a high amount of instruction-level as well as thread-level parallelism. The high-performance processing capabilities are integrated with a rich memory hierarchy providing high bandwidth through a large set of memory chips. For a set of applications with significantly different performance signatures we explore efficient use of this processor architecture.
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