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@INPROCEEDINGS{Adinets:189716,
      author       = {Adinets, Andrey and Baumeister, Paul F. and Böttiger, Hans
                      and Hater, Thorsten and Maurer, Thilo and Pleiter, Dirk and
                      Schenck, Wolfram and Schifano, Sebastiano Fabio},
      title        = {{P}erformance {E}valuation of {S}cientific {A}pplications
                      on {POWER}8},
      volume       = {8966},
      address      = {Cham},
      publisher    = {Springer International Publishing},
      reportid     = {FZJ-2015-02751},
      isbn         = {978-3-319-17247-7 (print)},
      series       = {Lecture Notes in Computer Science},
      pages        = {24 - 45},
      year         = {2015},
      comment      = {High Performance Computing Systems. Performance Modeling,
                      Benchmarking, and Simulation / ; Cham : Springer
                      International Publishing, 2015, Chapter 2 ; ISSN:
                      0302-9743=1611-3349 ; ISBN:
                      978-3-319-17247-7=978-3-319-17248-4 ;
                      doi:10.1007/978-3-319-17248-4},
      booktitle     = {High Performance Computing Systems.
                       Performance Modeling, Benchmarking, and
                       Simulation / ; Cham : Springer
                       International Publishing, 2015, Chapter
                       2 ; ISSN: 0302-9743=1611-3349 ; ISBN:
                       978-3-319-17247-7=978-3-319-17248-4 ;
                       doi:10.1007/978-3-319-17248-4},
      abstract     = {With POWER8 a new generation of POWER processors became
                      available. This architecture features a moderate number of
                      cores, each of which expose a high amount of
                      instruction-level as well as thread-level parallelism. The
                      high-performance processing capabilities are integrated with
                      a rich memory hierarchy providing high bandwidth through a
                      large set of memory chips. For a set of applications with
                      significantly different performance signatures we explore
                      efficient use of this processor architecture.},
      month         = {Nov},
      date          = {2014-11-16},
      organization  = {5th International Workshop on
                       Performance Modeling, Benchmarking and
                       Simulation of High Performance Computer
                       Systems (held as part of SC14), New
                       Orleans, LA (USA), 16 Nov 2014 - 16 Nov
                       2014},
      cin          = {JSC},
      ddc          = {004},
      cid          = {I:(DE-Juel1)JSC-20090406},
      pnm          = {513 - Supercomputer Facility (POF3-513) / SLNS - SimLab
                      Neuroscience (Helmholtz-SLNS)},
      pid          = {G:(DE-HGF)POF3-513 / G:(DE-Juel1)Helmholtz-SLNS},
      typ          = {PUB:(DE-HGF)8 / PUB:(DE-HGF)7},
      UT           = {WOS:000362507700002},
      doi          = {10.1007/978-3-319-17248-4_2},
      url          = {https://juser.fz-juelich.de/record/189716},
}