%0 Journal Article
%A Schmidt, Matthias
%A Schäfer, Anna
%A Minamisawa, Renato
%A Buca, Dan Mihai
%A Trellenkamp, Stefan
%A Hartmann, Jean-Michel
%A Zhao, Qing-Tai
%A Mantl, Siegfried
%T Line and Point Tunneling in Scaled Si/SiGe Heterostructure TFETs
%J IEEE electron device letters
%V 35
%N 7
%@ 1558-0563
%C New York, NY
%I IEEE
%M FZJ-2015-05218
%P 699 - 701
%D 2014
%X In this letter, we systematically investigate the impact of gate length and channel orientation on the electrical performance of tunneling field-effect transistors (TFETs). We fabricate and characterize Si/SiGe heterostructure TFETs with (p) -doped compressively strained Si0.5Ge0.5 source, intrinsic Si channel, and (n) -doped Si drain. We observe a linear relation of gate length, L (_{mathrm {mathbf {g}}}) , and ON-current, I (_{mathrm {{ON}}}) , which is the first experimental proof of line tunneling occurring in a TFET. TCAD simulations support our observations. After forming gas annealing, short-channel TFETs exhibit different I-V characteristics compared with long-channel devices due to better passivation.
%F PUB:(DE-HGF)16
%9 Journal Article
%U <Go to ISI:>//WOS:000338662100004
%R 10.1109/LED.2014.2320273
%U https://juser.fz-juelich.de/record/203232