Journal Article

FZJ-2015-05218

http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png Line and Point Tunneling in Scaled Si/SiGe Heterostructure TFETs

Schmidt, M. (Corresponding author) ; Schäfer, A.FZJ* ; Minamisawa, R. ; Buca, D. M.FZJ* ; Trellenkamp, S. ; Hartmann, J.-M. ; Zhao, Q.-T.FZJ* ; Mantl, S.FZJ*

2014
IEEE New York, NY

This record in other databases:  

Please use a persistent id in citations: doi:10.1109/LED.2014.2320273

Abstract: In this letter, we systematically investigate the impact of gate length and channel orientation on the electrical performance of tunneling field-effect transistors (TFETs). We fabricate and characterize Si/SiGe heterostructure TFETs with (p) -doped compressively strained Si0.5Ge0.5 source, intrinsic Si channel, and (n) -doped Si drain. We observe a linear relation of gate length, L (_{mathrm {mathbf {g}}}) , and ON-current, I (_{mathrm {{ON}}}) , which is the first experimental proof of line tunneling occurring in a TFET. TCAD simulations support our observations. After forming gas annealing, short-channel TFETs exhibit different I-V characteristics compared with long-channel devices due to better passivation.

---

Contributing Institute(s):

1. Halbleiter-Nanoelektronik (PGI-9)
2. PGI-8-PT (PGI-8-PT)

Research Program(s):

1. 521 - Controlling Electron Charge-Based Phenomena (POF3-521) (POF3-521)

Appears in the scientific report 2015

---

Database coverage:
Current Contents - Engineering, Computing and Technology ; IF < 5 ; JCR ; SCOPUS ; Science Citation Index ; Science Citation Index Expanded ; Thomson Reuters Master Journal List ; Web of Science Core Collection

---