TY  - JOUR
AU  - Schmidt, Matthias
AU  - Schäfer, Anna
AU  - Minamisawa, Renato
AU  - Buca, Dan Mihai
AU  - Trellenkamp, Stefan
AU  - Hartmann, Jean-Michel
AU  - Zhao, Qing-Tai
AU  - Mantl, Siegfried
TI  - Line and Point Tunneling in Scaled Si/SiGe Heterostructure TFETs
JO  - IEEE electron device letters
VL  - 35
IS  - 7
SN  - 1558-0563
CY  - New York, NY
PB  - IEEE
M1  - FZJ-2015-05218
SP  - 699 - 701
PY  - 2014
AB  - In this letter, we systematically investigate the impact of gate length and channel orientation on the electrical performance of tunneling field-effect transistors (TFETs). We fabricate and characterize Si/SiGe heterostructure TFETs with (p) -doped compressively strained Si0.5Ge0.5 source, intrinsic Si channel, and (n) -doped Si drain. We observe a linear relation of gate length, L (_{mathrm {mathbf {g}}}) , and ON-current, I (_{mathrm {{ON}}}) , which is the first experimental proof of line tunneling occurring in a TFET. TCAD simulations support our observations. After forming gas annealing, short-channel TFETs exhibit different I-V characteristics compared with long-channel devices due to better passivation.
LB  - PUB:(DE-HGF)16
UR  - <Go to ISI:>//WOS:000338662100004
DO  - DOI:10.1109/LED.2014.2320273
UR  - https://juser.fz-juelich.de/record/203232
ER  -