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001 | 203232 | ||
005 | 20210129220324.0 | ||
024 | 7 | _ | |2 doi |a 10.1109/LED.2014.2320273 |
024 | 7 | _ | |2 ISSN |a 0741-3106 |
024 | 7 | _ | |2 ISSN |a 1558-0563 |
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100 | 1 | _ | |0 P:(DE-HGF)0 |a Schmidt, Matthias |b 0 |e Corresponding author |
245 | _ | _ | |a Line and Point Tunneling in Scaled Si/SiGe Heterostructure TFETs |
260 | _ | _ | |a New York, NY |b IEEE |c 2014 |
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520 | _ | _ | |a In this letter, we systematically investigate the impact of gate length and channel orientation on the electrical performance of tunneling field-effect transistors (TFETs). We fabricate and characterize Si/SiGe heterostructure TFETs with (p) -doped compressively strained Si0.5Ge0.5 source, intrinsic Si channel, and (n) -doped Si drain. We observe a linear relation of gate length, L (_{mathrm {mathbf {g}}}) , and ON-current, I (_{mathrm {{ON}}}) , which is the first experimental proof of line tunneling occurring in a TFET. TCAD simulations support our observations. After forming gas annealing, short-channel TFETs exhibit different I-V characteristics compared with long-channel devices due to better passivation. |
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700 | 1 | _ | |0 P:(DE-HGF)0 |a Schäfer, Anna |b 1 |
700 | 1 | _ | |0 P:(DE-HGF)0 |a Minamisawa, Renato |b 2 |
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773 | _ | _ | |0 PERI:(DE-600)2034325-5 |a 10.1109/LED.2014.2320273 |g Vol. 35, no. 7, p. 699 - 701 |n 7 |p 699 - 701 |t IEEE electron device letters |v 35 |x 1558-0563 |y 2014 |
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