000037565 001__ 37565
000037565 005__ 20200610184813.0
000037565 0247_ $$2Handle$$a2128/263
000037565 0247_ $$2URI$$a263
000037565 037__ $$aPreJuSER-37565
000037565 0881_ $$aJuel-4139
000037565 088__ $$2JUEL$$aJuel-4139
000037565 1001_ $$0P:(DE-Juel1)128856$$aTrellenkamp, Stefan$$b0$$eCorresponding author$$uFZJ
000037565 245__ $$aEntwicklung und Charakterisierung vertikaler Double-Gate-MOS-Feldeffekttransistoren
000037565 260__ $$aJülich$$bForschungszentrum Jülich GmbH Zentralbibliothek, Verlag$$c2004
000037565 300__ $$aIV, 98 S.
000037565 3367_ $$0PUB:(DE-HGF)11$$2PUB:(DE-HGF)$$aDissertation / PhD Thesis
000037565 3367_ $$0PUB:(DE-HGF)3$$2PUB:(DE-HGF)$$aBook
000037565 3367_ $$02$$2EndNote$$aThesis
000037565 3367_ $$2DRIVER$$adoctoralThesis
000037565 3367_ $$2BibTeX$$aPHDTHESIS
000037565 3367_ $$2DataCite$$aOutput Types/Dissertation
000037565 3367_ $$2ORCID$$aDISSERTATION
000037565 4900_ $$0PERI:(DE-600)2414853-2$$817387$$aBerichte des Forschungszentrums Jülich$$v4139$$x0944-2952
000037565 502__ $$aAachen, Techn. Hochsch., Diss., 2003$$bDr. (FH)$$cTechn. Hochsch. Aachen$$d2003
000037565 500__ $$aRecord converted from VDB: 12.11.2012
000037565 520__ $$aPlanar MOS-field-effect transistors are common devices today used by the computer industry. When their miniaturization reaches its limit, alternate transistor concepts become necessary. In this thesis the development of vertical Double-Gate-MOS-field-effect transistors is presented. These types of transistors have a vertically aligned p-n-p junction (or n-p-n junction, respectively). Consequently, the source-drain current flows perpendicular with respect to the surface of the wafer. A Double-Gate-field-effect transistor is characterized by a very thin channel region framed by two parallel gates. Due to the symmetry of the structure and less bulk volume better gate control and hence better short channel behavior is expected, as well as an improved scaling potential. Nanostructuring of the transistor's active region is very challenging. Approximately 300 nm high and down to 30 nm wide silicon ridges are requisite. They can be realized using hydrogen silsesquioxane (HSQ) as inorganic high resolution resist for electron beam lithography. Structures defined in HSQ are then transferred with high anisotropy and selectivity into silicon using ICP-RIE (reactive ion etching with inductive coupled plasma). 25 nm wide and 330 nm high silicon ridges are achieved. Different transistor layouts are realized. The channel length is defined by epitaxial growth of doped silicon layers before or by ion implantation after nanostructuring, respectively. The transistors show source-drain currents up to 380 $\mu$A/$\mu$m and transconductances up to 480 pS/pm. Improved short channel behavior for decreasing width of the silicon ridges is demonstrated.
000037565 536__ $$0G:(DE-Juel1)FUEK252$$2G:(DE-HGF)$$aMaterialien, Prozesse und Bauelemente für die  Mikro- und Nanoelektronik$$cI01$$x0
000037565 655_7 $$aHochschulschrift$$xDissertation (FH)
000037565 8564_ $$uhttps://juser.fz-juelich.de/record/37565/files/Juel_4139_Trellenkamp.pdf$$yOpenAccess
000037565 909CO $$ooai:juser.fz-juelich.de:37565$$pdnbdelivery$$pVDB$$pdriver$$popen_access$$popenaire
000037565 915__ $$0StatID:(DE-HGF)0510$$2StatID$$aOpenAccess
000037565 9141_ $$y2004
000037565 9131_ $$0G:(DE-Juel1)FUEK252$$bInformation$$kI01$$lInformationstechnologie mit nanoelektronischen Systemen$$vMaterialien, Prozesse und Bauelemente für die  Mikro- und Nanoelektronik$$x0
000037565 9201_ $$0I:(DE-Juel1)VDB41$$d31.12.2006$$gISG$$kISG-1$$lInstitut für Halbleiterschichten und Bauelemente$$x0
000037565 970__ $$aVDB:(DE-Juel1)46546
000037565 980__ $$aVDB
000037565 980__ $$aJUWEL
000037565 980__ $$aConvertedRecord
000037565 980__ $$aphd
000037565 980__ $$aI:(DE-Juel1)PGI-9-20110106
000037565 980__ $$aUNRESTRICTED
000037565 980__ $$aFullTexts
000037565 9801_ $$aFullTexts
000037565 981__ $$aI:(DE-Juel1)PGI-9-20110106