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@PHDTHESIS{Trellenkamp:37565,
      author       = {Trellenkamp, Stefan},
      title        = {{E}ntwicklung und {C}harakterisierung vertikaler
                      {D}ouble-{G}ate-{MOS}-{F}eldeffekttransistoren},
      volume       = {4139},
      issn         = {0944-2952},
      school       = {Techn. Hochsch. Aachen},
      type         = {Dr. (FH)},
      address      = {Jülich},
      publisher    = {Forschungszentrum Jülich GmbH Zentralbibliothek, Verlag},
      reportid     = {PreJuSER-37565, Juel-4139},
      series       = {Berichte des Forschungszentrums Jülich},
      pages        = {IV, 98 S.},
      year         = {2004},
      note         = {Record converted from VDB: 12.11.2012; Aachen, Techn.
                      Hochsch., Diss., 2003},
      abstract     = {Planar MOS-field-effect transistors are common devices
                      today used by the computer industry. When their
                      miniaturization reaches its limit, alternate transistor
                      concepts become necessary. In this thesis the development of
                      vertical Double-Gate-MOS-field-effect transistors is
                      presented. These types of transistors have a vertically
                      aligned p-n-p junction (or n-p-n junction, respectively).
                      Consequently, the source-drain current flows perpendicular
                      with respect to the surface of the wafer. A
                      Double-Gate-field-effect transistor is characterized by a
                      very thin channel region framed by two parallel gates. Due
                      to the symmetry of the structure and less bulk volume better
                      gate control and hence better short channel behavior is
                      expected, as well as an improved scaling potential.
                      Nanostructuring of the transistor's active region is very
                      challenging. Approximately 300 nm high and down to 30 nm
                      wide silicon ridges are requisite. They can be realized
                      using hydrogen silsesquioxane (HSQ) as inorganic high
                      resolution resist for electron beam lithography. Structures
                      defined in HSQ are then transferred with high anisotropy and
                      selectivity into silicon using ICP-RIE (reactive ion etching
                      with inductive coupled plasma). 25 nm wide and 330 nm high
                      silicon ridges are achieved. Different transistor layouts
                      are realized. The channel length is defined by epitaxial
                      growth of doped silicon layers before or by ion implantation
                      after nanostructuring, respectively. The transistors show
                      source-drain currents up to 380 $\mu$A/$\mu$m and
                      transconductances up to 480 pS/pm. Improved short channel
                      behavior for decreasing width of the silicon ridges is
                      demonstrated.},
      cin          = {ISG-1},
      cid          = {I:(DE-Juel1)VDB41},
      pnm          = {Materialien, Prozesse und Bauelemente für die Mikro- und
                      Nanoelektronik},
      pid          = {G:(DE-Juel1)FUEK252},
      typ          = {PUB:(DE-HGF)11 / PUB:(DE-HGF)3},
      url          = {https://juser.fz-juelich.de/record/37565},
}