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001     37565
005     20200610184813.0
024 7 _ |2 Handle
|a 2128/263
024 7 _ |2 URI
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037 _ _ |a PreJuSER-37565
088 1 _ |a Juel-4139
088 _ _ |a Juel-4139
|2 JUEL
100 1 _ |0 P:(DE-Juel1)128856
|a Trellenkamp, Stefan
|b 0
|e Corresponding author
|u FZJ
245 _ _ |a Entwicklung und Charakterisierung vertikaler Double-Gate-MOS-Feldeffekttransistoren
260 _ _ |a Jülich
|b Forschungszentrum Jülich GmbH Zentralbibliothek, Verlag
|c 2004
300 _ _ |a IV, 98 S.
336 7 _ |0 PUB:(DE-HGF)11
|2 PUB:(DE-HGF)
|a Dissertation / PhD Thesis
336 7 _ |0 PUB:(DE-HGF)3
|2 PUB:(DE-HGF)
|a Book
336 7 _ |0 2
|2 EndNote
|a Thesis
336 7 _ |2 DRIVER
|a doctoralThesis
336 7 _ |2 BibTeX
|a PHDTHESIS
336 7 _ |2 DataCite
|a Output Types/Dissertation
336 7 _ |2 ORCID
|a DISSERTATION
490 0 _ |0 PERI:(DE-600)2414853-2
|8 17387
|a Berichte des Forschungszentrums Jülich
|v 4139
|x 0944-2952
500 _ _ |a Record converted from VDB: 12.11.2012
502 _ _ |a Aachen, Techn. Hochsch., Diss., 2003
|b Dr. (FH)
|c Techn. Hochsch. Aachen
|d 2003
520 _ _ |a Planar MOS-field-effect transistors are common devices today used by the computer industry. When their miniaturization reaches its limit, alternate transistor concepts become necessary. In this thesis the development of vertical Double-Gate-MOS-field-effect transistors is presented. These types of transistors have a vertically aligned p-n-p junction (or n-p-n junction, respectively). Consequently, the source-drain current flows perpendicular with respect to the surface of the wafer. A Double-Gate-field-effect transistor is characterized by a very thin channel region framed by two parallel gates. Due to the symmetry of the structure and less bulk volume better gate control and hence better short channel behavior is expected, as well as an improved scaling potential. Nanostructuring of the transistor's active region is very challenging. Approximately 300 nm high and down to 30 nm wide silicon ridges are requisite. They can be realized using hydrogen silsesquioxane (HSQ) as inorganic high resolution resist for electron beam lithography. Structures defined in HSQ are then transferred with high anisotropy and selectivity into silicon using ICP-RIE (reactive ion etching with inductive coupled plasma). 25 nm wide and 330 nm high silicon ridges are achieved. Different transistor layouts are realized. The channel length is defined by epitaxial growth of doped silicon layers before or by ion implantation after nanostructuring, respectively. The transistors show source-drain currents up to 380 $\mu$A/$\mu$m and transconductances up to 480 pS/pm. Improved short channel behavior for decreasing width of the silicon ridges is demonstrated.
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|a Materialien, Prozesse und Bauelemente für die Mikro- und Nanoelektronik
|c I01
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655 _ 7 |a Hochschulschrift
|x Dissertation (FH)
856 4 _ |u https://juser.fz-juelich.de/record/37565/files/Juel_4139_Trellenkamp.pdf
|y OpenAccess
909 C O |o oai:juser.fz-juelich.de:37565
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|v Materialien, Prozesse und Bauelemente für die Mikro- und Nanoelektronik
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914 1 _ |y 2004
915 _ _ |0 StatID:(DE-HGF)0510
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920 1 _ |0 I:(DE-Juel1)VDB41
|d 31.12.2006
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|l Institut für Halbleiterschichten und Bauelemente
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