%0 Conference Paper
%A Blaeser, S.
%A Richter, S.
%A Wirths, S.
%A Trellenkamp, S.
%A Buca, D.
%A Zhao, Q. T.
%A Mantl, Siegfried
%T Experimental demonstration of planar SiGe on Si TFETs with counter doped pocket
%I IEEE
%M FZJ-2016-06397
%@ 978-1-4799-6911-1
%P 297-300
%D 2015
%< EUROSOI-ULIS 2015
%X This paper presents both experimental and TCAD simulation results on a planar tunneling field-effect transistor (TFET) using compressively strained Si0.45Ge0.55 on Si. Introducing a counter doped pocket at the source tunnel junction in combination with a selective and self-adjusted silicidation to enlarge the tunneling area enables line tunneling aligned with the gate electric field which results in an enhanced band-to-band tunneling (BTBT) probability, increased on-current Ion and reduced inverse subthreshold swing (SS).
%B 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
%C 6 Dec 2015 - 8 Dec 2015, Bologna (Italy)
Y2 6 Dec 2015 - 8 Dec 2015
M2 Bologna, Italy
%F PUB:(DE-HGF)8 ; PUB:(DE-HGF)7
%9 Contribution to a conference proceedingsContribution to a book
%R 10.1109/ULIS.2015.7063832
%U https://juser.fz-juelich.de/record/821159