Contribution to a conference proceedings/Contribution to a book FZJ-2016-06397

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Experimental demonstration of planar SiGe on Si TFETs with counter doped pocket

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2015
IEEE
ISBN: 978-1-4799-6911-1

EUROSOI-ULIS 2015
2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), BolognaBologna, Italy, 6 Dec 2015 - 8 Dec 20152015-12-062015-12-08
IEEE 297-300 () [10.1109/ULIS.2015.7063832]

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Abstract: This paper presents both experimental and TCAD simulation results on a planar tunneling field-effect transistor (TFET) using compressively strained Si0.45Ge0.55 on Si. Introducing a counter doped pocket at the source tunnel junction in combination with a selective and self-adjusted silicidation to enlarge the tunneling area enables line tunneling aligned with the gate electric field which results in an enhanced band-to-band tunneling (BTBT) probability, increased on-current Ion and reduced inverse subthreshold swing (SS).


Contributing Institute(s):
  1. Halbleiter-Nanoelektronik (PGI-9)
  2. PGI-8-PT (PGI-8-PT)
Research Program(s):
  1. 521 - Controlling Electron Charge-Based Phenomena (POF3-521) (POF3-521)

Appears in the scientific report 2016
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 Record created 2016-11-18, last modified 2021-01-29



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