| Hauptseite > Publikationsdatenbank > Experimental demonstration of planar SiGe on Si TFETs with counter doped pocket > print |
| 001 | 821159 | ||
| 005 | 20210129224815.0 | ||
| 020 | _ | _ | |a 978-1-4799-6911-1 |
| 024 | 7 | _ | |a 10.1109/ULIS.2015.7063832 |2 doi |
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| 100 | 1 | _ | |a Blaeser, S. |0 P:(DE-HGF)0 |b 0 |
| 111 | 2 | _ | |a 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) |c Bologna |d 1/26/2015 - 1/28/2015 |w Italy |
| 245 | _ | _ | |a Experimental demonstration of planar SiGe on Si TFETs with counter doped pocket |
| 260 | _ | _ | |c 2015 |b IEEE |
| 295 | 1 | 0 | |a EUROSOI-ULIS 2015 |
| 300 | _ | _ | |a 297-300 |
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| 336 | 7 | _ | |a Contribution to a book |0 PUB:(DE-HGF)7 |2 PUB:(DE-HGF) |m contb |
| 520 | _ | _ | |a This paper presents both experimental and TCAD simulation results on a planar tunneling field-effect transistor (TFET) using compressively strained Si0.45Ge0.55 on Si. Introducing a counter doped pocket at the source tunnel junction in combination with a selective and self-adjusted silicidation to enlarge the tunneling area enables line tunneling aligned with the gate electric field which results in an enhanced band-to-band tunneling (BTBT) probability, increased on-current Ion and reduced inverse subthreshold swing (SS). |
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| 773 | _ | _ | |a 10.1109/ULIS.2015.7063832 |
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