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000821182 0247_ $$2doi$$a10.1109/ESSDERC.2016.7599684
000821182 037__ $$aFZJ-2016-06420
000821182 1001_ $$0P:(DE-HGF)0$$aHorst, Fabian$$b0$$eCorresponding author
000821182 1112_ $$aESSDERC 2016 - 46th European Solid-State Device Research Conference$$cLausanne$$d9/12/2016 - 9/15/2016$$wSwitzerland
000821182 245__ $$aImplementation of a DC compact model for double-gate Tunnel-FET based on 2D calculations and application in circuit simulation
000821182 260__ $$bIEEE$$c2016
000821182 300__ $$a456-459
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000821182 520__ $$aThis paper introduces a two-dimensional physics-based compact model for a double-gate (DG) Tunnel-FET (TFET) implemented in Verilog-A. The compact model is derived from an analytical model published in [1], [2], [3]. TCAD Sentaurus simulation data as well as measurement data are used to verify and show the flexibility of the modeling approach. Advantages and limitations of the compact model are analyzed and discussed. In order to demonstrate the numerical stability of the model, a basic circuit in form of a single stage inverter is simulated using complementary Tunnel-FET logic. The results of this circuit simulation are compared to measurements on fabricated inverters and are in good agreement.
000821182 536__ $$0G:(DE-HGF)POF3-521$$a521 - Controlling Electron Charge-Based Phenomena (POF3-521)$$cPOF3-521$$fPOF III$$x0
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000821182 7001_ $$0P:(DE-HGF)0$$aGraef, Michael$$b1
000821182 7001_ $$0P:(DE-HGF)0$$aHosenfeld, Fabian$$b2
000821182 7001_ $$0P:(DE-HGF)0$$aFarokhnejad, Atieh$$b3
000821182 7001_ $$0P:(DE-HGF)0$$aHain, Franziska$$b4
000821182 7001_ $$0P:(DE-Juel1)156277$$aLuong, Gia Vinh$$b5$$ufzj
000821182 7001_ $$0P:(DE-Juel1)128649$$aZhao, Qing-Tai$$b6$$ufzj
000821182 7001_ $$0P:(DE-HGF)0$$aIniguez, Benjamin$$b7
000821182 7001_ $$0P:(DE-HGF)0$$aKloes, Alexander$$b8
000821182 773__ $$a10.1109/ESSDERC.2016.7599684
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