TY  - CONF
AU  - Horst, Fabian
AU  - Graef, Michael
AU  - Hosenfeld, Fabian
AU  - Farokhnejad, Atieh
AU  - Hain, Franziska
AU  - Luong, Gia Vinh
AU  - Zhao, Qing-Tai
AU  - Iniguez, Benjamin
AU  - Kloes, Alexander
TI  - Implementation of a DC compact model for double-gate Tunnel-FET based on 2D calculations and application in circuit simulation
PB  - IEEE
M1  - FZJ-2016-06420
SN  - 978-1-5090-2969-3 
SP  - 456-459
PY  - 2016
AB  - This paper introduces a two-dimensional physics-based compact model for a double-gate (DG) Tunnel-FET (TFET) implemented in Verilog-A. The compact model is derived from an analytical model published in [1], [2], [3]. TCAD Sentaurus simulation data as well as measurement data are used to verify and show the flexibility of the modeling approach. Advantages and limitations of the compact model are analyzed and discussed. In order to demonstrate the numerical stability of the model, a basic circuit in form of a single stage inverter is simulated using complementary Tunnel-FET logic. The results of this circuit simulation are compared to measurements on fabricated inverters and are in good agreement.
T2  - ESSDERC 2016 - 46th European Solid-State Device Research Conference
CY  - 12 Sep 2016 - 15 Sep 2016, Lausanne (Switzerland)
Y2  - 12 Sep 2016 - 15 Sep 2016
M2  - Lausanne, Switzerland
LB  - PUB:(DE-HGF)8 ; PUB:(DE-HGF)7
DO  - DOI:10.1109/ESSDERC.2016.7599684
UR  - https://juser.fz-juelich.de/record/821182
ER  -