| Home > Publications database > Hybrid phase-change — Tunnel FET (PC-TFET) switch with subthreshold swing < 10mV/decade and sub-0.1 body factor: Digital and analog benchmarking > print |
| 001 | 827684 | ||
| 005 | 20210129225906.0 | ||
| 024 | 7 | _ | |a 10.1109/IEDM.2016.7838452 |2 doi |
| 037 | _ | _ | |a FZJ-2017-01797 |
| 100 | 1 | _ | |a Casu, E. A. |0 P:(DE-HGF)0 |b 0 |
| 111 | 2 | _ | |a 2016 IEEE International Electron Devices Meeting (IEDM) |c San Francisco |d 2016-12-03 - 2016-12-07 |w CA |
| 245 | _ | _ | |a Hybrid phase-change — Tunnel FET (PC-TFET) switch with subthreshold swing < 10mV/decade and sub-0.1 body factor: Digital and analog benchmarking |
| 260 | _ | _ | |c 2016 |b IEEE |
| 300 | _ | _ | |a 508-511 |
| 336 | 7 | _ | |a CONFERENCE_PAPER |2 ORCID |
| 336 | 7 | _ | |a Conference Paper |0 33 |2 EndNote |
| 336 | 7 | _ | |a INPROCEEDINGS |2 BibTeX |
| 336 | 7 | _ | |a conferenceObject |2 DRIVER |
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| 500 | _ | _ | |a ISBN 978-1-5090-3902-9 |
| 520 | _ | _ | |a In this paper we report the first hybrid Phase-Change — Tunnel FET (PC-TFET) device configurations for achieving a deep sub-thermionic steep subthreshold swing at room temperature and subthreshold power savings. The proposed hybrid device feedbacks the steep transition of Metal-Insulator transition in a VO2 structure into Gate or Source configurations of strained silicon nanowire Tunnel FETs, to achieve a switching with lon/Ioff better that 5.5×106 and with a subthreshold swing of 4.0 mV/dec at 25 °C. We demonstrate that the principle of PC-TFET switching relates to an internal amplification resulting in a sub-unity body factor, m, which is reduced to values below 0.1 for a current range larger than 2–3 decades. We report a full experimental digital and analog benchmarking of the new device and compare it with Tunnel FETs and CMOS. Remarkably, the PC-TFET can achieve analog figures of merit like gm/Id breaking the 40 V−1 limit of MOSFETs. We demonstrate and report the first buffered oscillator cell for neuromorphic computing exploiting the gate configuration of PC-TFET. |
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| 700 | 1 | _ | |a Vitale, W. A. |0 P:(DE-HGF)0 |b 1 |
| 700 | 1 | _ | |a Oliva, N. |0 P:(DE-HGF)0 |b 2 |
| 700 | 1 | _ | |a Rosca, T. |0 P:(DE-HGF)0 |b 3 |
| 700 | 1 | _ | |a Biswas, A. |0 P:(DE-HGF)0 |b 4 |
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| 773 | _ | _ | |a 10.1109/IEDM.2016.7838452 |
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