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| 001 | 829955 | ||
| 005 | 20210129230407.0 | ||
| 024 | 7 | _ | |2 doi |a 10.1109/LED.2017.2670642 |
| 024 | 7 | _ | |2 ISSN |a 0741-3106 |
| 024 | 7 | _ | |2 ISSN |a 1558-0563 |
| 024 | 7 | _ | |a WOS:000398905400010 |2 WOS |
| 037 | _ | _ | |a FZJ-2017-03559 |
| 082 | _ | _ | |a 620 |
| 100 | 1 | _ | |0 P:(DE-HGF)0 |a Schonhals, A. |b 0 |
| 245 | _ | _ | |a 3-bit Resistive RAM Write-Read Scheme Based on Complementary Switching Mechanism |
| 260 | _ | _ | |a New York, NY |b IEEE |c 2017 |
| 336 | 7 | _ | |2 DRIVER |a article |
| 336 | 7 | _ | |2 DataCite |a Output Types/Journal article |
| 336 | 7 | _ | |0 PUB:(DE-HGF)16 |2 PUB:(DE-HGF) |a Journal Article |b journal |m journal |s 1494590409_30052 |
| 336 | 7 | _ | |2 BibTeX |a ARTICLE |
| 336 | 7 | _ | |2 ORCID |a JOURNAL_ARTICLE |
| 336 | 7 | _ | |0 0 |2 EndNote |a Journal Article |
| 520 | _ | _ | |a While standard bipolar switching RRAM memory devices can be programmed into different resistance states, the complementary switching mechanism allows for two distinct switching locations that each can be programmed to these resistance states. In this letter, we present a technique to discriminate these switching locations and report on a novel scheme allowing for sub-μs pulse write and read of eight different logic states in Pt/Ta2O5/Ta/Pt devices by using only four different resistive states. Thus, in addition to the multilevel capability of bipolar switching devices, double the information can be stored and read in a single complementary switching device. |
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| 588 | _ | _ | |a Dataset connected to CrossRef |
| 700 | 1 | _ | |0 P:(DE-Juel1)142186 |a Mohr, J. |b 1 |
| 700 | 1 | _ | |0 P:(DE-HGF)0 |a Wouters, D. J. |b 2 |
| 700 | 1 | _ | |0 P:(DE-Juel1)131022 |a Waser, R. |b 3 |
| 700 | 1 | _ | |0 P:(DE-Juel1)158062 |a Menzel, S. |b 4 |
| 773 | _ | _ | |0 PERI:(DE-600)2034325-5 |a 10.1109/LED.2017.2670642 |g Vol. 38, no. 4, p. 449 - 452 |n 4 |p 449 - 452 |t IEEE electron device letters |v 38 |x 1558-0563 |y 2017 |
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| 914 | 1 | _ | |y 2017 |
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