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| Hauptseite > Publikationsdatenbank > 2-D Physics-Based Compact DC Modeling of Double-Gate Tunnel-FETs > print |
| Hauptseite > Publikationsdatenbank > 2-D Physics-Based Compact DC Modeling of Double-Gate Tunnel-FETs > print |
| 001 | 859059 | ||
| 005 | 20210130000149.0 | ||
| 024 | 7 | _ | |2 doi |a 10.1109/TED.2018.2856891 |
| 024 | 7 | _ | |2 ISSN |a 0018-9383 |
| 024 | 7 | _ | |2 ISSN |a 0096-2430 |
| 024 | 7 | _ | |2 ISSN |a 0197-6370 |
| 024 | 7 | _ | |2 ISSN |a 1557-9646 |
| 024 | 7 | _ | |2 ISSN |a 2379-8653 |
| 024 | 7 | _ | |2 ISSN |a 2379-8661 |
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| 037 | _ | _ | |a FZJ-2019-00010 |
| 082 | _ | _ | |a 620 |
| 100 | 1 | _ | |0 P:(DE-HGF)0 |a Horst, Fabian |b 0 |e Corresponding author |
| 245 | _ | _ | |a 2-D Physics-Based Compact DC Modeling of Double-Gate Tunnel-FETs |
| 260 | _ | _ | |a New York, NY |b IEEE |c 2019 |
| 336 | 7 | _ | |2 DRIVER |a article |
| 336 | 7 | _ | |2 DataCite |a Output Types/Journal article |
| 336 | 7 | _ | |0 PUB:(DE-HGF)16 |2 PUB:(DE-HGF) |a Journal Article |b journal |m journal |s 1547476865_19393 |
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| 520 | _ | _ | |a This paper presents the derivation of a compact dc modeling approach for the band-to-band tunneling current in double-gate tunnel-field effect transistors (TFETs). The physics-based model equations are solved in closed form by including 2-D effects and are implemented in the hardware description language Verilog-A. The verification of the model is done in two steps. First, the modeling approach is verified by TCAD Sentaurus simulation data of the band diagram, the transfer current, and the output current characteristics as well as the output conductance. The modeling results show a good agreement with the TCAD data. Then, measurement data of complementary nanowire gate-all-around TFET devices are utilized to verify the model and to show possible fields of application. As a part of the verification, the benefits and limitations are analyzed and discussed. The numerical stability and flexibility of the model are pointed out by performing simulations of a single-stage TFET inverter. |
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| 700 | 1 | _ | |0 P:(DE-HGF)0 |a Farokhnejad, Atieh |b 1 |
| 700 | 1 | _ | |0 P:(DE-Juel1)128649 |a Zhao, Qing-Tai |b 2 |u fzj |
| 700 | 1 | _ | |0 P:(DE-HGF)0 |a Iniguez, Benjamin |b 3 |
| 700 | 1 | _ | |0 P:(DE-HGF)0 |a Kloes, Alexander |b 4 |
| 773 | _ | _ | |0 PERI:(DE-600)2028088-9 |a 10.1109/TED.2018.2856891 |g p. 1 - 7 |n 1 |p 132-138 |t IEEE transactions on electron devices |v 66 |x 1557-9646 |y 2019 |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/859059/files/08423434.pdf |y Restricted |
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