%0 Conference Paper
%A Glass, S.
%A Schulte-Braucks, C.
%A Kibkalo, L.
%A Breuer, U.
%A Hartmann, J. M.
%A Buca, D.
%A Mantl, S.
%A Zhao, Q. T.
%T Examination of a new SiGe/Si heterostructure TFET concept based on vertical tunneling
%I IEEE
%M FZJ-2019-00019
%P 1-3
%D 2017
%< 2017 Fifth Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop (E3S)
%X This paper presents a Tunneling Field Effect Transistor concept with a vertical SiGe/Si hetero tunneling junction utilizing a design which promotes line tunneling in a source-gate overlap region. By contrast, the influence of parasitic point tunneling is marginal in the structure, resulting in a sharp turn-on. We show that the growth of a suitable layer stack and manufacturing a device is perfectly feasible and provide first electrical measurements serving as a proof of concept. The route to enhancing the performance by scaling device dimensions and adjusting the channel doping is examined by means of TCAD simulations.
%B 2017 Fifth Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop (E3S)
%C 19 Oct 2017 - 20 Oct 2017, Berkeley (USA)
Y2 19 Oct 2017 - 20 Oct 2017
M2 Berkeley, USA
%F PUB:(DE-HGF)8 ; PUB:(DE-HGF)7
%9 Contribution to a conference proceedingsContribution to a book
%R 10.1109/E3S.2017.8246169
%U https://juser.fz-juelich.de/record/859068