Contribution to a conference proceedings/Contribution to a book FZJ-2019-00019

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Examination of a new SiGe/Si heterostructure TFET concept based on vertical tunneling

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2017
IEEE

2017 Fifth Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop (E3S)
2017 Fifth Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop (E3S), BerkeleyBerkeley, USA, 19 Oct 2017 - 20 Oct 20172017-10-192017-10-20
IEEE 1-3 () [10.1109/E3S.2017.8246169]

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Abstract: This paper presents a Tunneling Field Effect Transistor concept with a vertical SiGe/Si hetero tunneling junction utilizing a design which promotes line tunneling in a source-gate overlap region. By contrast, the influence of parasitic point tunneling is marginal in the structure, resulting in a sharp turn-on. We show that the growth of a suitable layer stack and manufacturing a device is perfectly feasible and provide first electrical measurements serving as a proof of concept. The route to enhancing the performance by scaling device dimensions and adjusting the channel doping is examined by means of TCAD simulations.


Contributing Institute(s):
  1. Halbleiter-Nanoelektronik (PGI-9)
  2. Analytik (ZEA-3)
Research Program(s):
  1. 141 - Controlling Electron Charge-Based Phenomena (POF3-141) (POF3-141)

Appears in the scientific report 2018
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Institute Collections > PGI > PGI-9
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 Record created 2019-01-03, last modified 2021-01-30


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