TY  - CONF
AU  - Glass, S.
AU  - Schulte-Braucks, C.
AU  - Kibkalo, L.
AU  - Breuer, U.
AU  - Hartmann, J. M.
AU  - Buca, D.
AU  - Mantl, S.
AU  - Zhao, Q. T.
TI  - Examination of a new SiGe/Si heterostructure TFET concept based on vertical tunneling
PB  - IEEE
M1  - FZJ-2019-00019
SP  - 1-3
PY  - 2017
AB  - This paper presents a Tunneling Field Effect Transistor concept with a vertical SiGe/Si hetero tunneling junction utilizing a design which promotes line tunneling in a source-gate overlap region. By contrast, the influence of parasitic point tunneling is marginal in the structure, resulting in a sharp turn-on. We show that the growth of a suitable layer stack and manufacturing a device is perfectly feasible and provide first electrical measurements serving as a proof of concept. The route to enhancing the performance by scaling device dimensions and adjusting the channel doping is examined by means of TCAD simulations.
T2  - 2017 Fifth Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop (E3S)
CY  - 19 Oct 2017 - 20 Oct 2017, Berkeley (USA)
Y2  - 19 Oct 2017 - 20 Oct 2017
M2  - Berkeley, USA
LB  - PUB:(DE-HGF)8 ; PUB:(DE-HGF)7
DO  - DOI:10.1109/E3S.2017.8246169
UR  - https://juser.fz-juelich.de/record/859068
ER  -