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001     859068
005     20210130000152.0
024 7 _ |a 10.1109/E3S.2017.8246169
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100 1 _ |a Glass, S.
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111 2 _ |a 2017 Fifth Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop (E3S)
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|d 2017-10-19 - 2017-10-20
|w USA
245 _ _ |a Examination of a new SiGe/Si heterostructure TFET concept based on vertical tunneling
260 _ _ |c 2017
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295 1 0 |a 2017 Fifth Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop (E3S)
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520 _ _ |a This paper presents a Tunneling Field Effect Transistor concept with a vertical SiGe/Si hetero tunneling junction utilizing a design which promotes line tunneling in a source-gate overlap region. By contrast, the influence of parasitic point tunneling is marginal in the structure, resulting in a sharp turn-on. We show that the growth of a suitable layer stack and manufacturing a device is perfectly feasible and provide first electrical measurements serving as a proof of concept. The route to enhancing the performance by scaling device dimensions and adjusting the channel doping is examined by means of TCAD simulations.
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700 1 _ |a Schulte-Braucks, C.
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700 1 _ |a Kibkalo, L.
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700 1 _ |a Breuer, U.
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700 1 _ |a Hartmann, J. M.
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700 1 _ |a Buca, D.
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700 1 _ |a Mantl, S.
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700 1 _ |a Zhao, Q. T.
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773 _ _ |a 10.1109/E3S.2017.8246169
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