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000859083 0247_ $$2doi$$a10.1109/LED.2017.2695193
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000859083 1001_ $$0P:(DE-HGF)0$$aLiu, Chang$$b0
000859083 245__ $$aExperimental Investigation of ${C}$ – ${V}$ Characteristics of Si Tunnel FETs
000859083 260__ $$aNew York, NY$$bIEEE$$c2017
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000859083 520__ $$aThis letter presents an experimental capacitance-voltage C-V analysis for Si p-tunnel FETs (TFETs) fabricated on ultrathin body at various frequencies and temperatures. The capacitance distribution in TFETs is quite different compared with MOSFETs, due to different inversion charges partitioning between source and drain. Contrary to predictions from simulations, we provide experimental evidence for the first time that the contribution of the gate-to-source capacitance C gs to the total gate capacitance is much larger than expected, and even comparable to the gate-to-drain capacitance C gd at higher V ds and V g . Comparable values of C gs and C gd would imply that the Miller capacitance effect in TFETs-based circuits is less pronounced as predicted in simulations.
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000859083 7001_ $$0P:(DE-HGF)0$$aGlass, Stefan$$b1
000859083 7001_ $$0P:(DE-HGF)0$$aLuong, Gia Vinh$$b2
000859083 7001_ $$0P:(DE-Juel1)164261$$aNarimani, Keyvan$$b3$$ufzj
000859083 7001_ $$0P:(DE-Juel1)165600$$aHan, Qinghua$$b4$$ufzj
000859083 7001_ $$0P:(DE-Juel1)128639$$aTiedemann, Andreas$$b5
000859083 7001_ $$0P:(DE-HGF)0$$aFox, Alfred$$b6
000859083 7001_ $$0P:(DE-HGF)0$$aYu, Wenjie$$b7
000859083 7001_ $$0P:(DE-HGF)0$$aWang, Xi$$b8
000859083 7001_ $$0P:(DE-Juel1)128609$$aMantl, Siegfried$$b9$$ufzj
000859083 7001_ $$0P:(DE-Juel1)128649$$aZhao, Qing-Tai$$b10$$eCorresponding author
000859083 773__ $$0PERI:(DE-600)2034325-5$$a10.1109/LED.2017.2695193$$gVol. 38, no. 6, p. 818 - 821$$n6$$p818 - 821$$tIEEE electron device letters$$v38$$x1558-0563$$y2017
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