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000859084 037__ $$aFZJ-2019-00035
000859084 1001_ $$0P:(DE-HGF)0$$aHorst, Fabian$$b0$$eCorresponding author
000859084 1112_ $$a2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)$$cAthens$$d2017-04-03 - 2017-04-05$$wGreece
000859084 245__ $$aStatic noise margin analysis of 8T TFET SRAM cells using a 2D compact model adapted to measurement data of fabricated TFET devices
000859084 260__ $$bIEEE$$c2017
000859084 300__ $$a1-4
000859084 3367_ $$2ORCID$$aCONFERENCE_PAPER
000859084 3367_ $$033$$2EndNote$$aConference Paper
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000859084 520__ $$aIn this paper a static noise margin (SNM) analysis is done for an 8T SRAM cell build up with complementary tunnel-FETs (TFETs). The simulations are done with the help of a Verilog-A implemented 2D DC compact model for a double-gate (DG) TFET, published in [1]. The compact model is adapted to measurement data of fabricated nanowire (NW) GAA TFETs before analyzing the hold/read and write SNM of the 8T TFET SRAM cell. The impact of the ambipolar behavior as well as the unidirectional current of TFETs on the SRAM cell layout and simulation are taken into account and analyzed in this work. Furthermore, the impact of various supply voltages and device widths of the access transistors on the resulting SNM are investigated.
000859084 536__ $$0G:(DE-HGF)POF3-521$$a521 - Controlling Electron Charge-Based Phenomena (POF3-521)$$cPOF3-521$$fPOF III$$x0
000859084 588__ $$aDataset connected to CrossRef Conference
000859084 7001_ $$0P:(DE-HGF)0$$aGraef, Michael$$b1
000859084 7001_ $$0P:(DE-HGF)0$$aHosenfeld, Fabian$$b2
000859084 7001_ $$0P:(DE-HGF)0$$aFarokhnejad, Atieh$$b3
000859084 7001_ $$0P:(DE-HGF)0$$aLuong, Gia Vinh$$b4
000859084 7001_ $$0P:(DE-Juel1)128649$$aZhao, Qing-Tai$$b5$$eCollaboration author
000859084 7001_ $$0P:(DE-HGF)0$$aIniguez, Benjamin$$b6
000859084 7001_ $$0P:(DE-HGF)0$$aKloes, Alexander$$b7
000859084 773__ $$a10.1109/ULIS.2017.7962595
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000859084 9141_ $$y2018
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