Contribution to a conference proceedings

FZJ-2019-00035

http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png Static noise margin analysis of 8T TFET SRAM cells using a 2D compact model adapted to measurement data of fabricated TFET devices

Horst, F. (Corresponding author) ; Graef, M. ; Hosenfeld, F. ; Farokhnejad, A. ; Luong, G. V.FZJ* ; Zhao, Q.-T. (Collaboration author)FZJ* ; Iniguez, B. ; Kloes, A.

2017
IEEE

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Please use a persistent id in citations: doi:10.1109/ULIS.2017.7962595

Abstract: In this paper a static noise margin (SNM) analysis is done for an 8T SRAM cell build up with complementary tunnel-FETs (TFETs). The simulations are done with the help of a Verilog-A implemented 2D DC compact model for a double-gate (DG) TFET, published in [1]. The compact model is adapted to measurement data of fabricated nanowire (NW) GAA TFETs before analyzing the hold/read and write SNM of the 8T TFET SRAM cell. The impact of the ambipolar behavior as well as the unidirectional current of TFETs on the SRAM cell layout and simulation are taken into account and analyzed in this work. Furthermore, the impact of various supply voltages and device widths of the access transistors on the resulting SNM are investigated.

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Contributing Institute(s):

1. Halbleiter-Nanoelektronik (PGI-9)

Research Program(s):

1. 521 - Controlling Electron Charge-Based Phenomena (POF3-521) (POF3-521)

Appears in the scientific report 2018

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