TY  - CONF
AU  - Horst, Fabian
AU  - Graef, Michael
AU  - Hosenfeld, Fabian
AU  - Farokhnejad, Atieh
AU  - Luong, Gia Vinh
AU  - Iniguez, Benjamin
AU  - Kloes, Alexander
TI  - Static noise margin analysis of 8T TFET SRAM cells using a 2D compact model adapted to measurement data of fabricated TFET devices
PB  - IEEE
M1  - FZJ-2019-00035
SP  - 1-4
PY  - 2017
AB  - In this paper a static noise margin (SNM) analysis is done for an 8T SRAM cell build up with complementary tunnel-FETs (TFETs). The simulations are done with the help of a Verilog-A implemented 2D DC compact model for a double-gate (DG) TFET, published in [1]. The compact model is adapted to measurement data of fabricated nanowire (NW) GAA TFETs before analyzing the hold/read and write SNM of the 8T TFET SRAM cell. The impact of the ambipolar behavior as well as the unidirectional current of TFETs on the SRAM cell layout and simulation are taken into account and analyzed in this work. Furthermore, the impact of various supply voltages and device widths of the access transistors on the resulting SNM are investigated.
T2  - 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
CY  - 3 Apr 2017 - 5 Apr 2017, Athens (Greece)
Y2  - 3 Apr 2017 - 5 Apr 2017
M2  - Athens, Greece
LB  - PUB:(DE-HGF)8
DO  - DOI:10.1109/ULIS.2017.7962595
UR  - https://juser.fz-juelich.de/record/859084
ER  -