%0 Conference Paper
%A Narimani, K.
%A Glass, S.
%A Rieger, T.
%A Bernardy, P.
%A von den Driesch, N.
%A Mantl, S.
%A Zhao, Q. T.
%T Silicon tunnel FET with average subthreshold slope of 55mV/dec at low drain currents
%I IEEE
%M FZJ-2019-00036
%P 1-4
%D 2017
%X In this paper we present a silicon tunnel FET based on line-tunneling to achieve better subthreshold performance. It is shown that the device achieves I on /I off ratio of 5×10 4 considering I on (V on = V Ioff -0.5V) = 0.8×10 -8 μA/μm and an average SS of 55mV/dec over two orders of magnitude of I d . Furthermore, the analog figures of merit have been calculated and show that the transconductance efficiency g m /I d beats the MOSFET performance at lower currents.
%B 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
%C 3 Apr 2017 - 5 Apr 2017, Athens (Greece)
Y2 3 Apr 2017 - 5 Apr 2017
M2 Athens, Greece
%F PUB:(DE-HGF)8
%9 Contribution to a conference proceedings
%R 10.1109/ULIS.2017.7962605
%U https://juser.fz-juelich.de/record/859085