TY  - CONF
AU  - Narimani, K.
AU  - Glass, S.
AU  - Rieger, T.
AU  - Bernardy, P.
AU  - von den Driesch, N.
AU  - Mantl, S.
AU  - Zhao, Q. T.
TI  - Silicon tunnel FET with average subthreshold slope of 55mV/dec at low drain currents
PB  - IEEE
M1  - FZJ-2019-00036
SP  - 1-4
PY  - 2017
AB  - In this paper we present a silicon tunnel FET based on line-tunneling to achieve better subthreshold performance. It is shown that the device achieves I on /I off ratio of 5×10 4 considering I on (V on = V Ioff -0.5V) = 0.8×10 -8 μA/μm and an average SS of 55mV/dec over two orders of magnitude of I d . Furthermore, the analog figures of merit have been calculated and show that the transconductance efficiency g m /I d beats the MOSFET performance at lower currents.
T2  - 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
CY  - 3 Apr 2017 - 5 Apr 2017, Athens (Greece)
Y2  - 3 Apr 2017 - 5 Apr 2017
M2  - Athens, Greece
LB  - PUB:(DE-HGF)8
DO  - DOI:10.1109/ULIS.2017.7962605
UR  - https://juser.fz-juelich.de/record/859085
ER  -