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024 7 _ |a 10.1109/ULIS.2017.7962605
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037 _ _ |a FZJ-2019-00036
100 1 _ |a Narimani, K.
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111 2 _ |a 2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
|c Athens
|d 2017-04-03 - 2017-04-05
|w Greece
245 _ _ |a Silicon tunnel FET with average subthreshold slope of 55mV/dec at low drain currents
260 _ _ |c 2017
|b IEEE
300 _ _ |a 1-4
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520 _ _ |a In this paper we present a silicon tunnel FET based on line-tunneling to achieve better subthreshold performance. It is shown that the device achieves I on /I off ratio of 5×10 4 considering I on (V on = V Ioff -0.5V) = 0.8×10 -8 μA/μm and an average SS of 55mV/dec over two orders of magnitude of I d . Furthermore, the analog figures of merit have been calculated and show that the transconductance efficiency g m /I d beats the MOSFET performance at lower currents.
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700 1 _ |a Glass, S.
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700 1 _ |a Rieger, T.
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700 1 _ |a Zhao, Q. T.
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773 _ _ |a 10.1109/ULIS.2017.7962605
856 4 _ |u https://juser.fz-juelich.de/record/859085/files/07962605.pdf
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