%0 Journal Article
%A Biswas, Arnab
%A Luong, Gia Vinh
%A Chowdhury, M. Foysol
%A Alper, Cem
%A Udrea, Florin
%A Mantl, Siegfried
%A Ionescu, Adrian M.
%T Benchmarking of Homojunction Strained-Si NW Tunnel FETs for Basic Analog Functions
%J IEEE transactions on electron devices
%V 64
%N 4
%@ 1557-9646
%C New York, NY
%I IEEE
%M FZJ-2019-00039
%P 1441 - 1448
%D 2017
%X This paper reports a compact ambipolar model for homojunction strained-silicon (sSi) nanowire (NW) tunnel FETs (TFETs) capable of accurately describing both I-V and G-V characteristics in all regimes of operation, n- and p-ambipolarity, the superlinear onset of the output characteristics, and the temperature dependence. Experimental calibration on long channel (350 nm) complementary n- and p-type sSi NW TFETs has been performed to create the model, which is used to systematically benchmark the main analog figures of merit at device level: g m /Id, g m /g ds , f T and f T /I d V d , and their temperature dependence from 25°C to 125 °C. This allows for a direct comparison between 28-nm low-power Fully Depleted Silicon on Insulator (FD-SOI) CMOS node and 28-nm double-gate (DG) TFET. We demonstrate unique advantages of sSi DG TFET over CMOS, in terms of: 1) reduced temperature dependence of subthreshold swing; 2) higher transconductance per unit of current with peaks close to 40 V -1 , for currents lower than 10 nA/μm; and 3) higher unity gain frequency per unit power for currents below 10 nA/μm.
%F PUB:(DE-HGF)16
%9 Journal Article
%U <Go to ISI:>//WOS:000398818400005
%R 10.1109/TED.2017.2665527
%U https://juser.fz-juelich.de/record/859088