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000859088 1001_ $$0P:(DE-HGF)0$$aBiswas, Arnab$$b0$$eCorresponding author
000859088 245__ $$aBenchmarking of Homojunction Strained-Si NW Tunnel FETs for Basic Analog Functions
000859088 260__ $$aNew York, NY$$bIEEE$$c2017
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000859088 520__ $$aThis paper reports a compact ambipolar model for homojunction strained-silicon (sSi) nanowire (NW) tunnel FETs (TFETs) capable of accurately describing both I-V and G-V characteristics in all regimes of operation, n- and p-ambipolarity, the superlinear onset of the output characteristics, and the temperature dependence. Experimental calibration on long channel (350 nm) complementary n- and p-type sSi NW TFETs has been performed to create the model, which is used to systematically benchmark the main analog figures of merit at device level: g m /Id, g m /g ds , f T and f T /I d V d , and their temperature dependence from 25°C to 125 °C. This allows for a direct comparison between 28-nm low-power Fully Depleted Silicon on Insulator (FD-SOI) CMOS node and 28-nm double-gate (DG) TFET. We demonstrate unique advantages of sSi DG TFET over CMOS, in terms of: 1) reduced temperature dependence of subthreshold swing; 2) higher transconductance per unit of current with peaks close to 40 V -1 , for currents lower than 10 nA/μm; and 3) higher unity gain frequency per unit power for currents below 10 nA/μm.
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000859088 7001_ $$0P:(DE-HGF)0$$aLuong, Gia Vinh$$b1
000859088 7001_ $$0P:(DE-HGF)0$$aChowdhury, M. Foysol$$b2
000859088 7001_ $$0P:(DE-HGF)0$$aAlper, Cem$$b3
000859088 7001_ $$0P:(DE-Juel1)128649$$aZhao, Qing-Tai$$b4$$eCollaboration author
000859088 7001_ $$0P:(DE-HGF)0$$aUdrea, Florin$$b5
000859088 7001_ $$0P:(DE-Juel1)128609$$aMantl, Siegfried$$b6$$ufzj
000859088 7001_ $$0P:(DE-HGF)0$$aIonescu, Adrian M.$$b7
000859088 773__ $$0PERI:(DE-600)2028088-9$$a10.1109/TED.2017.2665527$$gVol. 64, no. 4, p. 1441 - 1448$$n4$$p1441 - 1448$$tIEEE transactions on electron devices$$v64$$x1557-9646$$y2017
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