% IMPORTANT: The following is UTF-8 encoded.  This means that in the presence
% of non-ASCII characters, it will not work with BibTeX 0.99 or older.
% Instead, you should use an up-to-date BibTeX implementation like “bibtex8” or
% “biber”.

@ARTICLE{Biswas:859088,
      author       = {Biswas, Arnab and Luong, Gia Vinh and Chowdhury, M. Foysol
                      and Alper, Cem and Udrea, Florin and Mantl, Siegfried and
                      Ionescu, Adrian M.},
      collaboration = {Zhao, Qing-Tai},
      title        = {{B}enchmarking of {H}omojunction {S}trained-{S}i {NW}
                      {T}unnel {FET}s for {B}asic {A}nalog {F}unctions},
      journal      = {IEEE transactions on electron devices},
      volume       = {64},
      number       = {4},
      issn         = {1557-9646},
      address      = {New York, NY},
      publisher    = {IEEE},
      reportid     = {FZJ-2019-00039},
      pages        = {1441 - 1448},
      year         = {2017},
      abstract     = {This paper reports a compact ambipolar model for
                      homojunction strained-silicon (sSi) nanowire (NW) tunnel
                      FETs (TFETs) capable of accurately describing both I-V and
                      G-V characteristics in all regimes of operation, n- and
                      p-ambipolarity, the superlinear onset of the output
                      characteristics, and the temperature dependence.
                      Experimental calibration on long channel (350 nm)
                      complementary n- and p-type sSi NW TFETs has been performed
                      to create the model, which is used to systematically
                      benchmark the main analog figures of merit at device level:
                      g m /Id, g m /g ds , f T and f T /I d V d , and their
                      temperature dependence from 25°C to 125 °C. This allows
                      for a direct comparison between 28-nm low-power Fully
                      Depleted Silicon on Insulator (FD-SOI) CMOS node and 28-nm
                      double-gate (DG) TFET. We demonstrate unique advantages of
                      sSi DG TFET over CMOS, in terms of: 1) reduced temperature
                      dependence of subthreshold swing; 2) higher transconductance
                      per unit of current with peaks close to 40 V -1 , for
                      currents lower than 10 nA/μm; and 3) higher unity gain
                      frequency per unit power for currents below 10 nA/μm.},
      cin          = {PGI-9},
      ddc          = {620},
      cid          = {I:(DE-Juel1)PGI-9-20110106},
      pnm          = {521 - Controlling Electron Charge-Based Phenomena
                      (POF3-521)},
      pid          = {G:(DE-HGF)POF3-521},
      typ          = {PUB:(DE-HGF)16},
      UT           = {WOS:000398818400005},
      doi          = {10.1109/TED.2017.2665527},
      url          = {https://juser.fz-juelich.de/record/859088},
}