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000860103 0247_ $$2doi$$a10.1145/3183352
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000860103 1001_ $$0P:(DE-HGF)0$$aBhattacharjee, Debjyoti$$b0
000860103 245__ $$aKogge-Stone Adder Realization using 1S1R Resistive Switching Crossbar Arrays
000860103 260__ $$aNew York, NY$$bAssociation for Computing Machinery$$c2018
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000860103 520__ $$aLow operating voltage, high storage density, non-volatile storage capabilities, and relative low access latencies have popularized memristive devices as storage devices. Memristors can be ideally used for in-memory computing in the form of hybrid CMOS nano-crossbar arrays. In-memory serial adders have been theoretically and experimentally proven for crossbar arrays. To harness the parallelism of memristive arrays, parallel-prefix adders can be effective. In this work, a novel mapping scheme for in-memory Kogge-Stone adder has been presented. The number of cycles increases logarithmically with the bit width N of the operands, i.e., O(log2N), and the device count is 5N. We verify the correctness of the proposed scheme by means of TaO× device model-based memristive simulations. We compare the proposed scheme with other proposed schemes in terms of number of cycle and number of devices
000860103 536__ $$0G:(DE-HGF)POF3-521$$a521 - Controlling Electron Charge-Based Phenomena (POF3-521)$$cPOF3-521$$fPOF III$$x0
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000860103 7001_ $$0P:(DE-HGF)0$$aSiemon, Anne$$b1
000860103 7001_ $$0P:(DE-HGF)0$$aLinn, Eike$$b2
000860103 7001_ $$0P:(DE-Juel1)158062$$aMenzel, Stephan$$b3$$ufzj
000860103 7001_ $$0P:(DE-HGF)0$$aChattopadhyay, Anupam$$b4
000860103 773__ $$0PERI:(DE-600)2193538-5$$a10.1145/3183352$$gVol. 14, no. 2, p. 1 - 14$$n2$$pArticle No. 30 $$tACM journal on emerging technologies in computing systems$$v14$$x1550-4832$$y2018
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