Contribution to a conference proceedings/Contribution to a book FZJ-2019-02051

http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png
SCIPHI Score-P and Cube Extensions for Intel Phi

 ;  ;  ;  ;  ;

2019
Springer International Publishing Cham
ISBN: 978-3-030-11987-4

Tools for High Performance Computing 2017
11th International Workshop on Parallel Tools for High Performance Computing, DresdenDresden, Germany, 11 Sep 2017 - 12 Sep 20172017-09-112017-09-12
Cham : Springer International Publishing 85-104 () [10.1007/978-3-030-11987-4_6]

This record in other databases:

Please use a persistent id in citations:   doi:

Abstract: The Knights Landing processors offers unique features with regards to memory hierarchy and vectorization capabilities. To improve tool support within these two areas, we present extensions to the Score-P measurement infrastructure and the Cube report explorer. With the Knights Landing edition, Intel introduced a new memory architecture, utilizing two types of memory, MCDRAM and DDR4 SDRAM. To assist the user in the decision where to place data structures, we introduce a MCDRAM candidate metric to the Cube report explorer. In addition we track all MCDRAM allocations through the hbwmalloc interface, providing memory metrics like leaked memory or the high-water mark on a per-region basis, as already known for the ubiquitous malloc/free. A Score-P metric plugin that records memory statistics via numastat on a per process level enables a timeline analysis using the Vampir toolset. To get the best performance out of , the large vector processing units need to be utilized effectively. The ratio between computation and data access and the vector processing unit (VPU) intensity are introduced as metrics to identify vectorization candidates on a per-region basis. The Portable Hardware Locality (hwloc) Broquedis et al. (hwloc: a generic framework for managing hardware affinities in hpc applications, 2010 [2]) library allows us to visualize the distribution of the KNL-specific performance metrics within the Cube report explorer, taking the hardware topology consisting of processor tiles and cores into account.


Contributing Institute(s):
  1. Jülich Supercomputing Center (JSC)
  2. JARA - HPC (JARA-HPC)
Research Program(s):
  1. 511 - Computational Science and Mathematical Methods (POF3-511) (POF3-511)
  2. ATMLPP - ATML Parallel Performance (ATMLPP) (ATMLPP)

Appears in the scientific report 2019
Database coverage:
OpenAccess
Click to display QR Code for this record

The record appears in these collections:
Document types > Events > Contributions to a conference proceedings
Document types > Books > Contribution to a book
JARA > JARA > JARA-JARA\-HPC
Workflow collections > Public records
Institute Collections > JSC
Publications database
Open Access

 Record created 2019-03-22, last modified 2025-03-14