% IMPORTANT: The following is UTF-8 encoded. This means that in the presence
% of non-ASCII characters, it will not work with BibTeX 0.99 or older.
% Instead, you should use an up-to-date BibTeX implementation like “bibtex8” or
% “biber”.
@ARTICLE{Siemon:873813,
author = {Siemon, Anne and Menzel, Stephan and Bhattacharjee,
Debjyoti and Waser, R. and Chattopadhyay, Anupam and Linn,
Eike},
title = {{S}klansky tree adder realization in 1{S}1{R} resistive
switching memory architecture},
journal = {European physical journal special topics},
volume = {228},
number = {10},
issn = {1951-6401},
address = {Heidelberg},
publisher = {Springer},
reportid = {FZJ-2020-01018},
pages = {2269 - 2285},
year = {2019},
abstract = {Redox-based resistive switches are an emerging class of
non-volatile memory and logic devices. Especially,
ultimately scaled transistor-less passive crossbar arrays
using a selector/resistive-switch (1S1R) configuration are
one of the most promising architectures. Due to the
scalability and the inherent logic and memory capabilities
of these devices, they are good candidates for
logic-in-memory approaches. But due to the memory
architecture, true parallelism can only be achieved by
either working on several arrays at the same time or at
multiple lines in an array at the same time. In this work, a
Sklansky tree adder is presented, which exploits the
parallelism of a single crossbar array. The functionality is
proven by means of memristive simulations using a
physics-based TaOx model. The circuit and device
requirements for this approach are discussed.},
cin = {PGI-7 / JARA-FIT},
ddc = {530},
cid = {I:(DE-Juel1)PGI-7-20110106 / $I:(DE-82)080009_20140620$},
pnm = {521 - Controlling Electron Charge-Based Phenomena
(POF3-521)},
pid = {G:(DE-HGF)POF3-521},
typ = {PUB:(DE-HGF)16},
UT = {WOS:000503216100028},
doi = {10.1140/epjst/e2019-900042-x},
url = {https://juser.fz-juelich.de/record/873813},
}