Journal Article

FZJ-2020-01018

http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png Sklansky tree adder realization in 1S1R resistive switching memory architecture

Siemon, A. (Corresponding author) ; Menzel, S.FZJ* ; Bhattacharjee, D. ; Waser, R.FZJ* ; Chattopadhyay, A. ; Linn, E.

2019
Springer Heidelberg

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Please use a persistent id in citations: doi:10.1140/epjst/e2019-900042-x

Abstract: Redox-based resistive switches are an emerging class of non-volatile memory and logic devices. Especially, ultimately scaled transistor-less passive crossbar arrays using a selector/resistive-switch (1S1R) configuration are one of the most promising architectures. Due to the scalability and the inherent logic and memory capabilities of these devices, they are good candidates for logic-in-memory approaches. But due to the memory architecture, true parallelism can only be achieved by either working on several arrays at the same time or at multiple lines in an array at the same time. In this work, a Sklansky tree adder is presented, which exploits the parallelism of a single crossbar array. The functionality is proven by means of memristive simulations using a physics-based TaOx model. The circuit and device requirements for this approach are discussed.

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Contributing Institute(s):

1. Elektronische Materialien (PGI-7)
2. JARA-FIT (JARA-FIT)

Research Program(s):

1. 521 - Controlling Electron Charge-Based Phenomena (POF3-521) (POF3-521)

Appears in the scientific report 2019

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Database coverage:
; Clarivate Analytics Master Journal List ; Current Contents - Physical, Chemical and Earth Sciences ; Ebsco Academic Search ; IF < 5 ; JCR ; SCOPUS ; Science Citation Index ; Science Citation Index Expanded ; Web of Science Core Collection

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