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| 001 | 873813 | ||
| 005 | 20210130004518.0 | ||
| 024 | 7 | _ | |a 10.1140/epjst/e2019-900042-x |2 doi |
| 024 | 7 | _ | |a 1951-6355 |2 ISSN |
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| 037 | _ | _ | |a FZJ-2020-01018 |
| 082 | _ | _ | |a 530 |
| 100 | 1 | _ | |a Siemon, Anne |0 P:(DE-HGF)0 |b 0 |e Corresponding author |
| 245 | _ | _ | |a Sklansky tree adder realization in 1S1R resistive switching memory architecture |
| 260 | _ | _ | |a Heidelberg |c 2019 |b Springer |
| 336 | 7 | _ | |a article |2 DRIVER |
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| 520 | _ | _ | |a Redox-based resistive switches are an emerging class of non-volatile memory and logic devices. Especially, ultimately scaled transistor-less passive crossbar arrays using a selector/resistive-switch (1S1R) configuration are one of the most promising architectures. Due to the scalability and the inherent logic and memory capabilities of these devices, they are good candidates for logic-in-memory approaches. But due to the memory architecture, true parallelism can only be achieved by either working on several arrays at the same time or at multiple lines in an array at the same time. In this work, a Sklansky tree adder is presented, which exploits the parallelism of a single crossbar array. The functionality is proven by means of memristive simulations using a physics-based TaOx model. The circuit and device requirements for this approach are discussed. |
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| 700 | 1 | _ | |a Menzel, Stephan |0 P:(DE-Juel1)158062 |b 1 |
| 700 | 1 | _ | |a Bhattacharjee, Debjyoti |0 P:(DE-HGF)0 |b 2 |
| 700 | 1 | _ | |a Waser, R. |0 P:(DE-Juel1)131022 |b 3 |
| 700 | 1 | _ | |a Chattopadhyay, Anupam |0 P:(DE-HGF)0 |b 4 |
| 700 | 1 | _ | |a Linn, Eike |0 P:(DE-HGF)0 |b 5 |
| 773 | _ | _ | |a 10.1140/epjst/e2019-900042-x |g Vol. 228, no. 10, p. 2269 - 2285 |0 PERI:(DE-600)2267176-6 |n 10 |p 2269 - 2285 |t European physical journal special topics |v 228 |y 2019 |x 1951-6401 |
| 856 | 4 | _ | |u https://juser.fz-juelich.de/record/873813/files/Siemon2019_Article_SklanskyTreeAdderRealizationIn.pdf |y Restricted |
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