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| Home > Publications database > Konzeptstudie für die System‐Architektur einer Datenverarbeitungs‐Einheit für eine MRT‐kompatible PET‐Insert Anwendung |
| Home > Publications database > Konzeptstudie für die System‐Architektur einer Datenverarbeitungs‐Einheit für eine MRT‐kompatible PET‐Insert Anwendung |
| Master Thesis | FZJ-2021-03582 |
2018
Abstract: To expand the accuracy of multimodal imaging techniques for the study of neurological diseases evolving new treatments, a new brain scanner will be developed supported by Helmholtz validation funding. Based on the latest digital photomultiplier detectors and current technological standards, a prototype diagnostic device is currently being developed as a combination of positron emission tomography (PET) and magnetic resonance imaging (MRI) technologies. The project is a cooperation between Forschungszentrum Jülich and RWTH Aachen and once finished, the device shall be marketed in concordance with the aim of the Helmholtz Validation funding. For the newly created PET insert to be operated at 7 T within the Siemens developed MRI system currently available at the Institute for Neurosciences and Medicine (INM‐4) of the Forschungszentrum Jülich, an FPGA‐based system serves as the central data processing interface between the used digital Silicon Photomultiplier (dSiPM) sensors and the data server. Based on the experience gained at the Central Institute for Engineering, Electronics and Analytics, ZEA‐2 ‐ Electronic Systems in handling neutron detectors and processing systems, this concept study has been used to extract critical features for consistent data processing and to identify suitable components. From the requirements of bandwidth, form factors and interoperability of the subsystems, a generic approach to a data processing unit has been developed. With the company N.A.T. GmbH and the supported μTCA standard, a robust and extensible concept for Ethernet‐based data transmission and preprocessing using the Virtex‐7 Zynq FPGA from Xilinx was developed. Simulations of the synthesized FPGA configuration proved the theoretical feasibility of the approach followed.
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