The European PILOT
Pilot using Independent Local & Open Technologies
| Grant period | 2021-12-01 - 2025-05-31 |
| Funding body | European Union |
| Call number | H2020-JTI-EuroHPC-2020-1 |
| Grant number | 101034126 |
| Further information: | CORDIS Homepage |
| Identifier | G:(EU-Grant)101034126 |
Note: Accelerators provide the majority of performance in modern High Performance Computing (HPC) systems and are the fundamental building blocks for Exascale systems. The European PILOT (Pilot using Independent Local & Open Technology) will be the first demonstration of two ALL European HPC and High Performance Data Analytics (HPDA) (AI, ML, DL) accelerators, designed, implemented, manufactured, and owned by Europe. The European PILOT combines open source software (SW) and open and proprietary hardware (HW) to deliver the first completely European full stack software, accelerator, and integrated ecosystem based on RISC-V accelerators coupled to any general purpose processor (CPU) via PCIe Gen 6.0 or CXL 3.0. This pilot will demonstrate key HPC and HPDA workloads and software stacks. The European PILOT is also the first to demonstrate an ALL European HPC ecosystem. The accelerators will be manufactured in the new European GlobalFoundries 12 nm advanced silicon technology, a major demonstration of European technology independence.
The European PILOT combines cutting edge research utilizing SW/HW co-design to demonstrate HPC and HPDA accelerators running key applications and libraries in a full software stack including middleware, runtimes, compilers, and tools for the emerging RISC-V ecosystem. The European PILOT is able to produce a full stack (SW and HW) research prototype by leveraging and extending the work done in multiple European projects like: EPI, MEEP, POP2 CoE, EuroEXA, and ExaNeSt. This pre-production system can only be realized with a combination of existing IP, HW emulation using FPGAs, and real ASIC prototypes that demonstrate the full stack feasibility of the hardware and software. Finally, while the applications we use span AI to HPC, the aggressive ASIC implementation (chiplet size and small geometry) will be the smallest technology node manufactured in Europe and can easily be adapted for a near-future HPC implementation.
Recent Publications
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Talk (non-conference) (Other)
Nassyr, S. (Corresponding author)FZJ*
GENERATING GEMM FOR RISC-V RVV (And other ISAs)
2023BLIS Retreat 2023, Austin, TXAustin, TX, USA, 28 Aug 2023 - 29 Aug 20232023-08-282023-08-29
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Poster (Other)
Nassyr, S. (Corresponding author)FZJ* ; Haghighi Mood, K.FZJ* ; Herten, A.FZJ*
Programmatically Reaching the Roof: Automated BLIS Kernel Generator for SVE and RVV
2023RISC-V Summit Europe 2023, BarcelonaBarcelona, Spain, 5 Jun 2023 - 9 Jun 20232023-06-052023-06-09
[10.34734/FZJ-2023-03437]
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