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@ARTICLE{Trensch:908993,
      author       = {Trensch, Guido and Morrison, Abigail},
      title        = {{A} {S}ystem-on-{C}hip {B}ased {H}ybrid {N}euromorphic
                      {C}ompute {N}ode {A}rchitecture for {R}eproducible
                      {H}yper-{R}eal-{T}ime {S}imulations of {S}piking {N}eural
                      {N}etworks},
      journal      = {Frontiers in neuroinformatics},
      volume       = {16},
      issn         = {1662-5196},
      address      = {Lausanne},
      publisher    = {Frontiers Research Foundation},
      reportid     = {FZJ-2022-02935},
      pages        = {884033},
      year         = {2022},
      abstract     = {Despite the great strides neuroscience has made in recent
                      decades, the underlying principles of brain function remain
                      largely unknown. Advancing the field strongly depends on the
                      ability to study large-scale neural networks and perform
                      complex simulations. In this context, simulations in
                      hyper-real-time are of high interest, as they would enable
                      both comprehensive parameter scans and the study of slow
                      processes, such as learning and long-term memory. Not even
                      the fastest supercomputer available today is able to meet
                      the challenge of accurate and reproducible simulation with
                      hyper-real acceleration. The development of novel
                      neuromorphic computer architectures holds out promise, but
                      the high costs and long development cycles for
                      application-specific hardware solutions makes it difficult
                      to keep pace with the rapid developments in neuroscience.
                      However, advances in System-on-Chip (SoC) device technology
                      and tools are now providing interesting new design
                      possibilities for application-specific implementations.
                      Here, we present a novel hybrid software-hardware
                      architecture approach for a neuromorphic compute node
                      intended to work in a multi-node cluster configuration. The
                      node design builds on the Xilinx Zynq-7000 SoC device
                      architecture that combines a powerful programmable logic
                      gate array (FPGA) and a dual-core ARM Cortex-A9 processor
                      extension on a single chip. Our proposed architecture makes
                      use of both and takes advantage of their tight coupling. We
                      show that available SoC device technology can be used to
                      build smaller neuromorphic computing clusters that enable
                      hyper-real-time simulation of networks consisting of tens of
                      thousands of neurons, and are thus capable of meeting the
                      high demands for modeling and simulation in neuroscience.},
      cin          = {JSC / INM-6 / IAS-6},
      ddc          = {610},
      cid          = {I:(DE-Juel1)JSC-20090406 / I:(DE-Juel1)INM-6-20090406 /
                      I:(DE-Juel1)IAS-6-20130828},
      pnm          = {5234 - Emerging NC Architectures (POF4-523) / 5111 -
                      Domain-Specific Simulation $\&$ Data Life Cycle Labs (SDLs)
                      and Research Groups (POF4-511) / ACA - Advanced Computing
                      Architectures (SO-092) / Open-Access-Publikationskosten
                      Forschungszentrum Jülich (OAPKFZJ) (491111487) / SLNS -
                      SimLab Neuroscience (Helmholtz-SLNS)},
      pid          = {G:(DE-HGF)POF4-5234 / G:(DE-HGF)POF4-5111 /
                      G:(DE-HGF)SO-092 / G:(GEPRIS)491111487 /
                      G:(DE-Juel1)Helmholtz-SLNS},
      typ          = {PUB:(DE-HGF)16},
      pubmed       = {35846779},
      UT           = {WOS:000827439200001},
      doi          = {10.3389/fninf.2022.884033},
      url          = {https://juser.fz-juelich.de/record/908993},
}